Forum Discussion
Yogesh
Occasional Contributor
Occasional ContributorCritical Warning: DDR Timing requirements not met
I have built a FPGA design with NIOS. But there are some timing warnings as below:
Critical Warning: DDR Timing requirements not met
Overwriting existing clock: <Clock Name>
When I was debuggin...
yoichiK_altera
Contributor
ContributorHi
Since you are receiving the DDT timing critical warning do you see the timing violation in Timing Analysis report ?
YogeshYes , There are about 12 paths violated inside SDRAM.
- yoichiK_altera
then why can not you close the timing ?
