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Yogesh's avatar
Yogesh
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5 years ago

Critical Warning: DDR Timing requirements not met

I have built a FPGA design with NIOS. But there are some timing warnings as below: Critical Warning: DDR Timing requirements not met Overwriting existing clock: <Clock Name> When I was debuggin...
yoichiK_altera's avatar
yoichiK_altera
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5 years ago

Hi

Since you are receiving the DDT timing critical warning do you see the timing violation in Timing Analysis report ?

  • Yogesh's avatar
    Yogesh
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Yes , There are about 12 paths violated inside SDRAM.

    • yoichiK_altera's avatar
      yoichiK_altera
      Icon for Contributor rankContributor
      5 years ago

      then why can not you close the timing ?