Forum Discussion
Yogesh
Occasional Contributor
Occasional ContributorCritical Warning: DDR Timing requirements not met
I have built a FPGA design with NIOS. But there are some timing warnings as below:
Critical Warning: DDR Timing requirements not met
Overwriting existing clock: <Clock Name>
When I was debuggin...
YogeshOccasional Contributor
Occasional ContributorYes , There are about 12 paths violated inside SDRAM.
yoichiK_altera
Contributor
Contributorthen why can not you close the timing ?
