convert avalon bus to AXI4-Lite

1) You can drag and drop signals to make pin assignments in the Pin Planner. Dedicated clock input pins are indicated with a little waveform symbol on them.

2) The PLL is an IP you can parameterize so you can set what the output frequency should be based on the input frequency.

3) There's no need to export any files from the Pin Planner. The assignments are placed in the .qsf file as Richard mentioned. And a .sdc file is for timing constraints. It has nothing to do with pin assignments other than using the names of the top-level I/O signals for creating I/O timing constraints.

4) Again, not clear if you are still talking about pin assignments or if you need help with timing constraints. Check the Timing Analyzer user guide for the latter: https://www.intel.com/content/www/us/en/docs/programmable/683068.html

5) .sdc file is added to the Timing Analyzer settings in the Settings dialog box from the Assignments menu. And as mentioned, pin assignments are automatically added to the .qsf file as you make them in the Pin Planner.