Connecting a USB<->rs232(uart) module to the de-0 nano via GPIO

Since you comment you are a newbie, I'll provide some feedback on your design proposal and offer an alternative.

Your project/proposal:

What is the task? Are you responsible for the FPGA communications, or is that just a means-to-an-end? Is the main task related to the polynomial coefficients and whatever those coefficients are controlling?

As far as the communications aspect goes, your solution would work fine, however, it may involve more work than is really necessary. Here's what you would do:

1. Connect the two boards together.

a) The serial board looks like some sort of FTDI breakout board with USB and a header. It should be receiving power from the USB port, so there should be *no* reason for you to connect power pins from that board to the DE0-nano.

b) Check that your RS232 board output is 3.3V logic - not 5V logic (the DE0-nano cannot handle 5V signals).

c) Connect the TX and RX pins from your serial board to two GPIO pins on your DE0-nano, and connect a ground pin between the two boards (so that they both agree on voltages).

2. Create an FPGA system containing a NIOS II processor, a UART, and your custom logic and connect that UART to the GPIO pins.

3. Write NIOS II software to receive data over the serial port, and write the coefficients into your custom logic.

4. Write the host software to send data to the NIOS II.

While all this is pretty straightforward, since you are new to this, it might take you a while to get to grips with all the details.

An alternative implementation is to implement the communications using the USB-Blaster connection that already exists between your board and your PC. Read through this tutorial

http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial

The tutorial contains all the code you need for communications with a Qsys or SOPC System.

Continue to ask questions and the readers of this forum will provide feedback.

Cheers,

Dave

It's just a means-to-an-end, the main task is related with the polynomial coefficients(generating primitive polynomials), but my teacher said that in the future(on the masters degree project) I would need asynchronous data transfer and the USB-blaster has some problems with it(is this true?, I guess UART is all about asynchronous data transfer so if the USB blaster supports it...), so it seems the connection is *part* of the project(but if i can't get it to work then I will probably consider your idea).

a) This is correct, it is in fact a FTDI FT232BM on the board. I downloaded the VCP(com port) driver from the ftdi site but my PC can't seem to see the device(this is why I thought that maybe i would have to supply power to it), don't know if it's broken for some reason, will try to find out.

b) It says that the board supports 3.3V and 5V

If I understand correctly, the idea is to use the NIOS II processor on the de-0 nano but this would be impossible as I MUST use VHDL in this project(unless the NIOS is only used to connect the gpio pins to the inputs of my vhdl symbol). This also rises another question I had, if I somehow correctly connected the boards, what type of data would I receive on the de-0 nano(rs232-how do I then convert this to std_logic_vector which I use in the logic for example)? For example if what kind of data would I need to send from the c++ program(int, char, coefficients are 0,1,2)? Does this even depend on the de-0 or on the ftdi controller? Again forgive my low knowledge about this subject(I thought it would be enough to connect the GPIO pins in a BDF file to the symbol block in quartus).

Thanks a lot for the help, the first post was very informative and you were kind enough answer the questions about my idea(even though it might not be, as you stated, the most efficient one).

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It's just a means-to-an-end, the main task is related with the polynomial coefficients (generating primitive polynomials), but my teacher said that in the future(on the masters degree project) I would need asynchronous data transfer and the USB-blaster has some problems with it (is this true?, I guess UART is all about asynchronous data transfer so if the USB blaster supports it...), so it seems the connection is *part* of the project (but if i can't get it to work then I will probably consider your idea).

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I have not had any major issues with using the USB-Blaster as shown in the tutorial.

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a) This is correct, it is in fact a FTDI FT232BM on the board. I downloaded the VCP(com port) driver from the ftdi site but my PC can't seem to see the device(this is why I thought that maybe i would have to supply power to it), don't know if it's broken for some reason, will try to find out.

b) It says that the board supports 3.3V and 5V

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What is the part number of the board? I'll take a look for you.

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If I understand correctly, the idea is to use the NIOS II processor on the de-0 nano but this would be impossible as I MUST use VHDL in this project (unless the NIOS is only used to connect the gpio pins to the inputs of my vhdl symbol).

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Look at the block diagram on the tutorial link above.

Your coefficients block and logic would be implemented in VHDL. The control interface to that logic could either be via an Avalon-MM slave interface, i.e., it would be a slave in the block diagram like the SRAM and PIO blocks. You could also create an interface, where the PIO blocks are used to transfer the coefficients, or using dual-ported SRAM, you write the coefficients to SRAM, and then you write to a PIO to tell your logic the coefficients are 'ready', and it goes and reads them. This latter idea eliminates you having to understand how to create an Avalon-MM component - you just need to write a state machine to read from SRAM. Regardless of what you want to do, you will be able to get help here on the forum.

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This also rises another question I had, if I somehow correctly connected the boards, what type of data would I receive on the de-0 nano(rs232-how do I then convert this to std_logic_vector which I use in the logic for example)? For example if what kind of data would I need to send from the c++ program(int, char, coefficients are 0,1,2)? Does this even depend on the de-0 or on the ftdi controller? Again forgive my low knowledge about this subject(I thought it would be enough to connect the GPIO pins in a BDF file to the symbol block in quartus).

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This is why I suggested using the tried-and-tested USB-Blaster route :)

If you use a NIOS II processor plus UART, then you have to do less work. The FTDI device is a USB-to-Serial (or USB-to-UART) which takes bytes you write to the serial port driver (whatever you type into Hyperterminal, or a buffer you pass to write()) and serializes them as 8-bits, no parity, 1 stop bit at 115k2 baud (or whatever you configure your FTDI device to transmit). The UART in your NIOS II system gets configured to expect that same data. As every byte is received over the USB-to-UART interface, the UART buffers it, and generates an interrupt to your NIOS II processor. You then read that data and use software to parse it. What gets sent over the serial port is up to your software.

For example, I use this very simple ASCII protocol

r <addr>\n

w <addr> <data>\n

where <addr> and <data> are hex values.

I can run hyper-terminal on my PC and talk to a DE0-nano using a C232HM (an FT232H) cable.

In my case, I have coded the UART interface entirely in VHDL, and implemented a UART-to-Avalon-MM master. I could give you the code, but that would spoil the learning process for you. So if you want to go the "interface-entirely-in-VHDL" route, then I can provide help when you get stuck.

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Thanks a lot for the help, the first post was very informative and you were kind enough answer the questions about my idea(even though it might not be, as you stated, the most efficient one).

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Take my advice and follow this philosophy:

"Get it working, then get it right"

which is to say, take the easy way out (minimum time/effort solution) whenever you can, until you get the entire system working.

For example, you have a design goal, with the primary task of getting the logic that uses your coefficients working. Is that logic finished? If not, don't fall into the trap of spending a lot of time learning how to implement the communications interface. You may waste valuable time on that task, without realizing you have a bigger problem in the coefficients logic.

Take the time now to go through the USB-Blaster tutorial. Add your logic and control it with the PIO blocks, eg., 8-bits data and a couple of control bits to indicate coefficient updates etc.

Get that working - even if its clunky or slow, it still works.

Then go back and optimize. We can talk about the RS232 interface in VHDL at that time.

Cheers,

Dave

I guess the part number is ZL1USB_B. The pdf(in polish) that came with the board is in the attachemnt. Also, this is a more detailed picture:

https://www.alteraforum.com/forum/attachment.php?attachmentid=6524

The problem is that the module doesn't show up in the device list(I'm starting to think it may be broken) after connecting it via USB(im 100% sure the cable is fine as I used it for a printer), as it should according to the instruction in the 2nd attachment.

Now about the coefficient logic (and the "Get it working, then get it right" part:) )(no idea why I didn't ask this question on this forum before), it's mostly done(and gives good results) except for 2 problems(this is strictly VHDL/quartus so maybe I should ask this in another suboard):

a) I couldn't seem to make my logic block work with my own defined type. When I created my own type TYPE gf3 IS ( '0', '1', '2' ); and TYPE gf3_vector IS ARRAY ( NATURAL RANGE <> ) OF gf3; quartus wouldn't allow me to create a block file citing that it does not support own types for ports(??). I also came to the same problem when trying to simulate the logic in modelsim, so I am currently using the std_logic_vector type to model the polynomials(0, 1, Z), but I'm concerned about how the 'Z' symbol will be implemented on the de-0 nano(so I practically don't have an idea on how to efficiently represent the GF3 polynomials).

b) I wasn't able to find a method to dynamically change the size of the port std_logic_vector, ie. I wanted to have a std_logic_vector of the size n depending on the size of the input polynomial(which would be different for each polynomial). I am currently using something like this:

generic

(

n : natural := 29;

) ;

port

(

poly_in: in std_logic_vector(n downto 0);

newpoly1: out std_logic_vector(n downto 0) := (others => '0')

) ;

but this is obviosly temporary(I used this option to simulate in modelsim), as I can only change the vector size before compilation and not dynamically with different input polynomials. I'm pretty sure this is something easy to do but haven't been able to find a suitable solution. Currently I'm very busy this week so I'll read the guide you sent me and then continue the project next weekend probably. Again, thanks for all the help.

First, lets talk about the USB-to-Serial board.

I guess you have no experience with hardware, since the reason it did not work is fairly obvious. When something does not work, the first thing you look for is "where does the power come from?". Look at the schematic on p2 zl1usb_b.pdf. FTDI devices can be powered from USB or from a local power source. If you opened an FTDI data sheet you would see the different ways to power the device. Looking at this board, you can see there is a VCC for power, and a VCCIO for output signal power. Table 1 indicates that VCC = 5V and VCCIO = 3.3V or 5V. I cannot read Polish, but it might even say that those voltages are required :)

Without 5V and 3.3V, this particular board will not show up on the USB bus. VCC_SYS on the DE0-nano connector is derived from the 5V USB signal, so you can use that for VCC, and use the De0-nano VCC3P3 to power the 3.3V pins.

That should be sufficient to get your FTDI device powered and recognized by your PC. The device will work fine under Windows 7.

Now, regarding your coefficient logic. Your description is not very clear. Could you please post some example code, along with a testbench that is supposed to exercise the code.

Cheers,

Dave

So I was right in the first post about the power supply:D It works fine now and I have installed the drivers etc, now comes the tricky part the whole interface you were talking about. I consider either of the two ideas: "You could also create an interface, where the PIO blocks are used to transfer the coefficients, or using dual-ported SRAM, you write the coefficients to SRAM, and then you write to a PIO to tell your logic the coefficients are 'ready', and it goes and reads them." and am more inclined to the usage of the SRAM, is there any tutorial on how to do this(for example how to use SRAM to read the GPIO inputs in quartus, how to connect the SRAM to the PIO, I found some information about the PIO at johnloomis.org/NiosII/pio/PIO_Core.html).

About the VHDL code I attached an example two files with some of the problems I encountered.

a) In the case I try to make a symbol file for the bbb entity I get the error

Error (10017): Can't create symbol/include/instantiation/component file for entity "bbb" because port "poly1" are not currently supported by the Quartus II symbol/include/instantiation/component file generator

Error (10017): Can't create symbol/include/instantiation/component file for entity "bbb" because port "poly2" are not currently supported by the Quartus II symbol/include/instantiation/component file generator

I was very suprised as I thought all normal types in std( like std_logic_vector) were in theory user types but from what I understand from the error message that is not the case, beacause of this I was currently using std_logic_vector(with the coefficients modeled by 0 1 Z) but think that using the Z symbol in the project isn't a good idea. I'm guessing this is about the inputs/outputs only being able to use 0, 1? In that case should I use 00 01 10 11 to model it?

b)Another problem I ran into was setting the length of my input vectors, I wanted the length of the vector correspond to the length of the polynomial(I would have the length as an input integer n) but I wasn't able to find a way to do this(so I was just manually setting the lengths before simulating in modelsim)(the idea is commentated in bbb.vhd).

c)My final problem is the lengths of an array of arrays(this is somewhat related to the last question). I had this type that I need in the library(it's an argument in a funtion) but I would have to somehow send the n integer from the entity file to the library file.type std_logic_tab is array (natural range <>) of std_logic_vector(n downto 0);

Does this even have sense? Can I somehow declare this type not using the n downto 0(I tried this but quartus says I can'h have an unconstraind array)?

Only now do I start seeing how much there is to learn still with all this FPGA development(just started;p).

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... am more inclined to the usage of the SRAM, is there any tutorial on how to do this(for example how to use SRAM to read the GPIO inputs in quartus, how to connect the SRAM to the PIO, I found some information about the PIO at johnloomis.org/NiosII/pio/PIO_Core.html).

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Create an instance of a single-port RAM component, and then create a testbench to read and write to it. Then create a dual-port version. That'll help you get the hang of the components.

Typically I'll use the MegaWizard to create a component, then look inside the created logic. If the MegaWizard has just created a wrapper over something simple (in this case an altsyncram), then I just pull the altsyncram out, and re-work it so that the generics are grouped nicely. You'll see what I mean when you generate some RAMs.

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I was currently using std_logic_vector(with the coefficients modeled by 0 1 Z)

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If Z is supposed to be used internal to the FPGA, then no, you don't want to use it, use 00b, 01b, 10b (or 11b) for your three state logic.

For some of your other questions, you need to look at other peoples code to see how they've solved problems. This tutorial has some VHDL that might use some of the language features you need:

http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf

http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial_src.zip

Cheers,

Dave

Ok, so I eventually got a bit confused after reading each post a couple times, on what I need and what I don't. I want to create a new SOPC and don't know which components I finally need. If I understand correctly, I need:

A Nios II processor to control the blocks.

A UART to connect from one side to the GPIO and the other side to the SDRAM(do I need a PIO to send the coeffidients to the SDRAM from the UART?).

A PIO block to read from the SDRAM and send the coefficients to the logic block(and let the block know when to read them).

Fred

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I want to create a new SOPC and don't know which components I finally need.

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Well, if you describe to yourself "how" your system is supposed to work, eg., draw a flow chart, you'll quickly figure out what you "need".

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If I understand correctly, I need:

A Nios II processor to control the blocks.

A UART to connect from one side to the GPIO and the other side to the SDRAM(do I need a PIO to send the coeffidients to the SDRAM from the UART?).

A PIO block to read from the SDRAM and send the coefficients to the logic block(and let the block know when to read them).

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Based on the fact that you want to use the serial module (rather than JTAG), and you want to expend minimal effort on hardware design, then you want an SOPC system with a NIOS II processor, and a UART. That UART would connect to the GPIO that in turn connect to your external module.

Work with that until you get "Hello World!" working.

Then modify the SOPC system to add whatever you want to test. Whether it is PIO or RAM depends on how you interface to your hardware.

I know there is a lot to come to grips with, but don't get intimidated, start off simple/minimal - NIOS II + UART.

Once you get that working, you'll feel a lot more comfortable in the development environment.

Cheers,

Dave

Ok, so I'm starting to get a bit crazy:D Atm, I just want to send a 8 bit vector from my computer, "not" it, and send it back.

So I started with creating a SOPC

https://www.alteraforum.com/forum/attachment.php?attachmentid=6556

And now I have no idea, do I use the new component option inside the SOPC(with the "not" logic, I attached the file but it's really simple) or outside the SOPC. I currently have something like this

https://www.alteraforum.com/forum/attachment.php?attachmentid=6557

Which shows me that I can connect the UART to the GPIO pins, but how do I then send the received data(from the uart) to my logic block? Reading the manual that came with the de-0 nano didn't really help as they just used the sopc to run simple C program on the de-0 nano while using the Jtag UART. So my main problem would be how can I access the converted UART data? Peering into the vhdl file generated by the SOPC builder there is about a million signals and my guess would be that one of them would be used as the converted data from the UART?

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Based on the fact that you want to use the serial module (rather than JTAG).

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Well, since it's the more complicated idea maybe I can learn more from it:)

Thanks for all the newbie info,

Fred