Honored Contributor
Honored ContributorSo I was right in the first post about the power supply:D It works fine now and I have installed the drivers etc, now comes the tricky part the whole interface you were talking about. I consider either of the two ideas: "You could also create an interface, where the PIO blocks are used to transfer the coefficients, or using dual-ported SRAM, you write the coefficients to SRAM, and then you write to a PIO to tell your logic the coefficients are 'ready', and it goes and reads them." and am more inclined to the usage of the SRAM, is there any tutorial on how to do this(for example how to use SRAM to read the GPIO inputs in quartus, how to connect the SRAM to the PIO, I found some information about the PIO at johnloomis.org/NiosII/pio/PIO_Core.html).
About the VHDL code I attached an example two files with some of the problems I encountered. a) In the case I try to make a symbol file for the bbb entity I get the error Error (10017): Can't create symbol/include/instantiation/component file for entity "bbb" because port "poly1" are not currently supported by the Quartus II symbol/include/instantiation/component file generator Error (10017): Can't create symbol/include/instantiation/component file for entity "bbb" because port "poly2" are not currently supported by the Quartus II symbol/include/instantiation/component file generator I was very suprised as I thought all normal types in std( like std_logic_vector) were in theory user types but from what I understand from the error message that is not the case, beacause of this I was currently using std_logic_vector(with the coefficients modeled by 0 1 Z) but think that using the Z symbol in the project isn't a good idea. I'm guessing this is about the inputs/outputs only being able to use 0, 1? In that case should I use 00 01 10 11 to model it? b)Another problem I ran into was setting the length of my input vectors, I wanted the length of the vector correspond to the length of the polynomial(I would have the length as an input integer n) but I wasn't able to find a way to do this(so I was just manually setting the lengths before simulating in modelsim)(the idea is commentated in bbb.vhd). c)My final problem is the lengths of an array of arrays(this is somewhat related to the last question). I had this type that I need in the library(it's an argument in a funtion) but I would have to somehow send the n integer from the entity file to the library file.type std_logic_tab is array (natural range <>) of std_logic_vector(n downto 0); Does this even have sense? Can I somehow declare this type not using the n downto 0(I tried this but quartus says I can'h have an unconstraind array)? Only now do I start seeing how much there is to learn still with all this FPGA development(just started;p).
