Connect inclk of PLL to output port of alt_inbuf

Hi,

preventing unlimited routing of PLL clock input is basically intentional action of Quartus fitter, not imposed by lack of connectivity. See discussion in this thread Is there any option to generate 100MHZ clock without PLL in max10 device - Intel Community

I understand that Altera/Intel didn't release "unlimited" PLL inclk routing because it may reduce PLL performance and cause PLL failure under circumstances. Even if it works seamlessly in many cases (I guess so), the remaining problems could cause a big load for Intel support and possibly compromize product reputation.

Regards
Frank