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Sushmita's avatar
Sushmita
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Can Verification BFM IP example design (Quartus 16.1) be run on Quartus 18.1 version?

Hi,

I want to run Verification IP BFM example design in qsys. It supports 16.1 version of quartus.

I am using quartus 18.1 version with Arria 10 device support installed as required by the design.

To generate a simulation testbench, I am changing the options as mentioned in the instructions of the below mentioned document. When i try to save the design and generate HDL, it gives the errors as " the design is not writable".

My question is as follows:

1) Can I run the example design with quartus 18.1 version?

2) If yes, how can I resolve the error or steps i should follow?

3) If not, is there any other updated document, design tat i must refer?

Please find page 188 of the following document for avalon mm single master design:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_avalon_verification_ip.pdf

Regards

Ssrb

5 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    6 years ago

    I'm guessing you mean page 178 (or 174 for Verilog) instead of 188, because the document you link to only has 184 pages!

    Assuming you downloaded the example design mentioned there, check writability on the directory where you unzipped it. Also check the length of the path to get to that directory. Really long paths can cause weird issues like this as well.

    If you could post the exact errors and messages leading up to the error, that would help as well.

    #iwork4intel

    • Sushmita's avatar
      Sushmita
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago

      Hi,

      For me the document is : "Avalon Verification IP Suite", User Guide, Updated for Intel® Quartus® Prime Design Suite: 20.1.

      The link i have attached opens a doc of 198 pages!

      Page 188 has the heading - 19.1.1. Running the Verilog HDL Testbench for a Single Avalon-MM Master and Slave Pair

      I have used the same path as given. While opening qsys, I get the warnings that clock, master and slave used ip 18.1 instead of 16.1, also in the info the preferred simulation language is set to "none"

      According to the instructions in the second image attached,, i must set simulation language to verilog. Here i can't save the changes made. (as shown in the image).

      Hope this data is sufficient.

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    6 years ago

    This is what I see when I click the link you posted:

    But anyway, I'd try moving the files to a different location. Do you have administrator access? The files are in the administrator downloads folder. If you can't write the files, you can't enable the simulation option and you can't generate the files.

    #iwork4intel

    • Sushmita's avatar
      Sushmita
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago

      Okay, i will try to move the folder and check once.

      I will get back to you.

      Thank you.