Occasional Contributor
Super ContributorI'm guessing you mean page 178 (or 174 for Verilog) instead of 188, because the document you link to only has 184 pages!
Assuming you downloaded the example design mentioned there, check writability on the directory where you unzipped it. Also check the length of the path to get to that directory. Really long paths can cause weird issues like this as well.
If you could post the exact errors and messages leading up to the error, that would help as well.
#iwork4intel
Occasional ContributorHi,
For me the document is : "Avalon Verification IP Suite", User Guide, Updated for Intel® Quartus® Prime Design Suite: 20.1.
The link i have attached opens a doc of 198 pages!
Page 188 has the heading - 19.1.1. Running the Verilog HDL Testbench for a Single Avalon-MM Master and Slave Pair
I have used the same path as given. While opening qsys, I get the warnings that clock, master and slave used ip 18.1 instead of 16.1, also in the info the preferred simulation language is set to "none"
According to the instructions in the second image attached,, i must set simulation language to verilog. Here i can't save the changes made. (as shown in the image).
Hope this data is sufficient.
