I have quite a few questions for the BeMicro SDK, but one at a time. The support material is pretty lacking and doesn't even include a pin assignment. I made one based on the schematics, but when I try to instantiate the DDR memory controller, it fails to place with the message: "Error: Cannot place I/O pin mem_dq[8] in pin location E8 -- I/O standard assigned to pin requires VREF value and VREF pin corresponding to pin location not available Error: Cannot place I/O pin mem_dq[9] in pin location E7 -- I/O standard assigned to pin requires VREF value and VREF pin corresponding to pin location not available Error: Cannot place I/O pin mem_dq[10] in pin location E6 -- I/O standard assigned to pin requires VREF value and VREF pin corresponding to pin location not available Error: Cannot place I/O pin mem_dq[11] in pin location A7 -- I/O standard assigned to pin requires VREF value and VREF pin corresponding to pin location not available Error: Cannot place I/O pin mem_dq[12] in pin location B7 -- I/O standard assigned to pin requires VREF value and VREF pin corresponding to pin location not available Error: Cannot place I/O pin mem_dq[13] in pin location B6 -- I/O standard assigned to pin requires VREF value and VREF pin corresponding to pin location not available Error: Cannot place I/O pin mem_dq[14] in pin location B5 -- I/O standard assigned to pin requires VREF value and VREF pin corresponding to pin location not available Error: Cannot place I/O pin mem_dq[15] in pin location A5 -- I/O standard assigned to pin requires VREF value and VREF pin corresponding to pin location not available ..." Looking at the schematics, I do see that the lower half of mem_dq lives in Bank 7 which does indeed have its VREF hooked up to 1.8 V, however Bank 8 has its VREF assigned to chip select! Is this a bug? Any suggestions to how to workaround it (other than wasting half the SDRAM and only use the lower-order byte)? Thanks Tommy

FWIW, dropping the higher order byte didn't help: --- Quote Start --- Error: Cannot place I/O pin mem_dqs[0] in pin location C8 -- I/O standard assigned to pin requires VREF value and VREF pin corresponding to pin location not available --- Quote End --- I've shot a mail at Arrow hoping to make some progress.

Any progress with your efforts? I'm currently trying to get answers for the BeMicro SDK from Arrow too. Their BSP is a joke (at least what I have been able to find), it does not even include support for DDR RAM, microSD, or Ethernet. But there is a pin assignment file, it is just hard to find. In the Zip file "BeMicro_SDK_Lab_Materials_v1_22" there is a sub folder "Optional_HW_Lab". In that folder there is another zip that contains a file "pin_assignments.tcl" that has what you might need. David

Thanks. The original zip file with support material didn't contain the Optional_HW_Lab subfolder. I did get an answer (multiple actually) from Arrow. The essence is that the Altera DDR controller doesn't support mobile DDR so they used 3rd party IP (same for the SDcard). This was an unexpected upset and makes the BeMicro SDK a lot less attractive, unless some alternative way of using the onboard DDR SDRAM becomes available. I'm still considering rolling my own controller, but it's outside my comfort zone and would be a non-trivial undertaking.

I've ran into the exact same problem today. Spent lots of time until I found this post. Thanks for posting the answer from Arrow.

I got an answer promising more information within the next few days. Apparently the biggest problem is the Micron memory requires micron IP. They weren't clear if they were going to release a version of the project with their own IP or if they were going to release a version that has standalone IP but we will see. I think their web page is more than a little misleading for this product.

BeMicro SDK: PIN C6 (VREFB8N0) is assigned to RAM_CS#

17 Replies

Altera_Forum
Honored Contributor
15 years ago
davidsmoot,

Could you please post the settings that you used in the sopc builder for the Microtronix SDRAM controller? I'm looking for Bank Address bits, Row Address bits, Column Address bits, Total Number of Discrete Memory Devices, etc. that are in the Memory Tab of the parameters. That would be appreciated.

Thanks
Altera_Forum
Honored Contributor
15 years ago
I have the BeMicro SDK, and downloaded the Microtronix memory controller. I built my system using SOPC, and instantiated the system in my high-level entity (VHDL). When I compile I get the following errors, and I am not sure what is the problem.

Any help is highly appreciated!

Error: The DDIO_OUT WYSIWYG primitive "bemicro_sys:bemicro_sys_inst|mtx_avalon_sdram_0:the_mtx_avalon_sdram_0|mtx_sdram_controller:sdram|mtx_sdram_ddr_bidir:\gen_ddr_datapath:gen_cyclone_datapath:gen_ddr_dqs_groups:0:gen_ddr_master_dqs|altddio_bidir:\gen_ciii_dq:gen_dq_loop:0:ciii_dq|ddio_bidir_86k:auto_generated|ddio_outa[0]" feeding the node "bemicro_sys:bemicro_sys_inst|mtx_avalon_sdram_0:the_mtx_avalon_sdram_0|mtx_sdram_controller:sdram|mtx_sdram_ddr_bidir:\gen_ddr_datapath:gen_cyclone_datapath:gen_ddr_dqs_groups:0:gen_ddr_master_dqs|altddio_bidir:\gen_ciii_dq:gen_dq_loop:0:ciii_dq|ddio_bidir_86k:auto_generated|input_cell_h[0]" has multiple fan-outs
Error: The DDIO_OUT WYSIWYG primitive "bemicro_sys:bemicro_sys_inst|mtx_avalon_sdram_0:the_mtx_avalon_sdram_0|mtx_sdram_controller:sdram|mtx_sdram_ddr_bidir:\gen_ddr_datapath:gen_cyclone_datapath:gen_ddr_dqs_groups:0:gen_ddr_master_dqs|altddio_bidir:\gen_ciii_dq:gen_dq_loop:1:ciii_dq|ddio_bidir_86k:auto_generated|ddio_outa[0]" feeding the node "bemicro_sys:bemicro_sys_inst|mtx_avalon_sdram_0:the_mtx_avalon_sdram_0|mtx_sdram_controller:sdram|mtx_sdram_ddr_bidir:\gen_ddr_datapath:gen_cyclone_datapath:gen_ddr_dqs_groups:0:gen_ddr_master_dqs|altddio_bidir:\gen_ciii_dq:gen_dq_loop:1:ciii_dq|ddio_bidir_86k:auto_generated|input_cell_h[0]" has multiple fan-outs
Error: The DDIO_OUT WYSIWYG primitive "bemicro_sys:bemicro_sys_inst|mtx_avalon_sdram_0:the_mtx_avalon_sdram_0|mtx_sdram_controller:sdram|mtx_sdram_ddr_bidir:\gen_ddr_datapath:gen_cyclone_datapath:gen_ddr_dqs_groups:0:gen_ddr_master_dqs|altddio_bidir:\gen_ciii_dq:gen_dq_loop:2:ciii_dq|ddio_bidir_86k:auto_generated|ddio_outa[0]" feeding the node "bemicro_sys:bemicro_sys_inst|mtx_avalon_sdram_0:the_mtx_avalon_sdram_0|mtx_sdram_controller:sdram|mtx_sdram_ddr_bidir:\gen_ddr_datapath:gen_cyclone_datapath:gen_ddr_dqs_groups:0:gen_ddr_master_dqs|altddio_bidir:\gen_ciii_dq:gen_dq_loop:2:ciii_dq|ddio_bidir_86k:auto_generated|input_cell_h[0]" has multiple fan-outs
Error: The DDIO_OUT WYSIWYG primitive "bemicro_sys:bemicro_sys_inst|mtx_avalon_sdram_0:the_mtx_avalon_sdram_0|mtx_sdram_controller:sdram|mtx_sdram_ddr_bidir:\gen_ddr_datapath:gen_cyclone_datapath:gen_ddr_dqs_groups:0:gen_ddr_master_dqs|altddio_bidir:\gen_ciii_dq:gen_dq_loop:3:ciii_dq|ddio_bidir_86k:auto_generated|ddio_outa[0]" feeding the node "bemicro_sys:bemicro_sys_inst|mtx_avalon_sdram_0:the_mtx_avalon_sdram_0|mtx_sdram_controller:sdram|mtx_sdram_ddr_bidir:\gen_ddr_datapath:gen_cyclone_datapath:gen_ddr_dqs_groups:0:gen_ddr_master_dqs|altddio_bidir:\gen_ciii_dq:gen_dq_loop:3:ciii_dq|ddio_bidir_86k:auto_generated|input_cell_h[0]" has multiple fan-outs
Error: The DDIO_OUT WYSIWYG primitive "bemicro_sys:bemicro_sys_inst|mtx_avalon_sdram_0:the_mtx_avalon_sdram_0|mtx_sdram_controller:sdram|mtx_sdram_ddr_bidir:\gen_ddr_datapath:gen_cyclone_datapath:gen_ddr_dqs_groups:0:gen_ddr_master_dqs|altddio_bidir:\gen_ciii_dq:gen_dq_loop:4:ciii_dq|ddio_bidir_86k:auto_generated|ddio_outa[0]" feeding the node "bemicro_sys:bemicro_sys_inst|mtx_avalon_sdram_0:the_mtx_avalon_sdram_0|mtx_sdram_controller:sdram|mtx_sdram_ddr_bidir:\gen_ddr_datapath:gen_cyclone_datapath:gen_ddr_dqs_groups:0:gen_ddr_master_dqs|altddio_bidir:\gen_ciii_dq:gen_dq_loop:4:ciii_dq|ddio_bidir_86k:auto_generated|input_cell_h[0]" has multiple fan-outs
Error: The DDIO_OUT WYSIWYG primitive "bemicro_sys:bemicro_sys_inst|mtx_avalon_sdram_0:the_mtx_avalon_sdram_0|mtx_sdram_controller:sdram|mtx_sdram_ddr_bidir:\gen_ddr_datapath:gen_cyclone_datapath:gen_ddr_dqs_groups:0:gen_ddr_master_dqs|altddio_bidir:\gen_ciii_dq:gen_dq_loop:5:ciii_dq|ddio_bidir_86k:auto_generated|ddio_outa[0]" feeding the node "bemicro_sys:bemicro_sys_inst|mtx_avalon_sdram_0:the_mtx_avalon_sdram_0|mtx_sdram_controller:sdram|mtx_sdram_ddr_bidir:\gen_ddr_datapath:gen_cyclone_datapath:gen_ddr_dqs_groups:0:gen_ddr_master_dqs|altddio_bidir:\gen_ciii_dq:gen_dq_loop:5:ciii_dq|ddio_bidir_86k:auto_generated|input_cell_h[0]" has multiple fan-outs
Error: The DDIO_OUT WYSIWYG primitive "bemicro_sys:bemicro_sys_inst|mtx_avalon_sdram_0:the_mtx_avalon_sdram_0|mtx_sdram_controller:sdram|mtx_sdram_ddr_bidir:\gen_ddr_datapath:gen_cyclone_datapath:gen_ddr_dqs_groups:0:gen_ddr_master_dqs|altddio_bidir:\gen_ciii_dq:gen_dq_loop:6:ciii_dq|ddio_bidir_86k:auto_generated|ddio_outa[0]" feeding the node "bemicro_sys:bemicro_sys_inst|mtx_avalon_sdram_0:the_mtx_avalon_sdram_0|mtx_sdram_controller:sdram|mtx_sdram_ddr_bidir:\gen_ddr_datapath:gen_cyclone_datapath:gen_ddr_dqs_groups:0:gen_ddr_master_dqs|altddio_bidir:\gen_ciii_dq:gen_dq_loop:6:ciii_dq|ddio_bidir_86k:auto_generated|input_cell_h[0]" has multiple fan-outs
Error: The DDIO_OUT WYSIWYG primitive "bemicro_sys:bemicro_sys_inst|mtx_avalon_sdram_0:the_mtx_avalon_sdram_0|mtx_sdram_controller:sdram|mtx_sdram_ddr_bidir:\gen_ddr_datapath:gen_cyclone_datapath:gen_ddr_dqs_groups:0:gen_ddr_master_dqs|altddio_bidir:\gen_ciii_dq:gen_dq_loop:7:ciii_dq|ddio_bidir_86k:auto_generated|ddio_outa[0]" feeding the node "bemicro_sys:bemicro_sys_inst|mtx_avalon_sdram_0:the_mtx_avalon_sdram_0|mtx_sdram_controller:sdram|mtx_sdram_ddr_bidir:\gen_ddr_datapath:gen_cyclone_datapath:gen_ddr_dqs_groups:0:gen_ddr_master_dqs|altddio_bidir:\gen_ciii_dq:gen_dq_loop:7:ciii_dq|ddio_bidir_86k:auto_generated|input_cell_h[0]" has multiple fan-outs
Error: The DDIO_OUT WYSIWYG primitive "bemicro_sys:bemicro_sys_inst|mtx_avalon_sdram_0:the_mtx_avalon_sdram_0|mtx_sdram_controller:sdram|mtx_sdram_ddr_bidir:\gen_ddr_datapath:gen_cyclone_datapath:gen_ddr_dqs_groups:0:gen_gen_ddr_slave_dqs:1:gen_ddr_slave_dqs|altddio_bidir:\gen_ciii_dq:gen_dq_loop:0:ciii_dq|ddio_bidir_86k:auto_generated|ddio_outa[0]" feeding the node "bemicro_sys:bemicro_sys_inst|mtx_avalon_sdram_0:the_mtx_avalon_sdram_0|mtx_sdram_controller:sdram|mtx_sdram_ddr_bidir:\gen_ddr_datapath:gen_cyclone_datapath:gen_ddr_dqs_groups:0:gen_gen_ddr_slave_dqs:1:gen_ddr_slave_dqs|altddio_bidir:\gen_ciii_dq:gen_dq_loop:0:ciii_dq|ddio_bidir_86k:auto_generated|input_cell_h[0]" has multiple fan-outs
Error: The DDIO_OUT WYSIWYG primitive "bemicro_sys:bemicro_sys_inst|mtx_avalon_sdram_0:the_mtx_avalon_sdram_0|mtx_sdram_controller:sdram|mtx_sdram_ddr_bidir:\gen_ddr_datapath:gen_cyclone_datapath:gen_ddr_dqs_groups:0:gen_gen_ddr_slave_dqs:1:gen_ddr_slave_dqs|altddio_bidir:\gen_ciii_dq:gen_dq_loop:1:ciii_dq|ddio_bidir_86k:auto_generated|ddio_outa[0]" feeding the node "bemicro_sys:bemicro_sys_inst|mtx_avalon_sdram_0:the_mtx_avalon_sdram_0|mtx_sdram_controller:sdram|mtx_sdram_ddr_bidir:\gen_ddr_datapath:gen_cyclone_datapath:gen_ddr_dqs_groups:0:gen_gen_ddr_slave_dqs:1:gen_ddr_slave_dqs|altddio_bidir:\gen_ciii_dq:gen_dq_loop:1:ciii_dq|ddio_bidir_86k:auto_generated|input_cell_h[0]" has multiple fan-outs
Error: The DDIO_OUT WYSIWYG primitive "bemicro_sys:bemicro_sys_inst|mtx_avalon_sdram_0:the_mtx_avalon_sdram_0|mtx_sdram_controller:sdram|mtx_sdram_ddr_bidir:\gen_ddr_datapath:gen_cyclone_datapath:gen_ddr_dqs_groups:0:gen_gen_ddr_slave_dqs:1:gen_ddr_slave_dqs|altddio_bidir:\gen_ciii_dq:gen_dq_loop:2:ciii_dq|ddio_bidir_86k:auto_generated|ddio_outa[0]" feeding the node "bemicro_sys:bemicro_sys_inst|mtx_avalon_sdram_0:the_mtx_avalon_sdram_0|mtx_sdram_controller:sdram|mtx_sdram_ddr_bidir:\gen_ddr_datapath:gen_cyclone_datapath:gen_ddr_dqs_groups:0:gen_gen_ddr_slave_dqs:1:gen_ddr_slave_dqs|altddio_bidir:\gen_ciii_dq:gen_dq_loop:2:ciii_dq|ddio_bidir_86k:auto_generated|input_cell_h[0]" has multiple fan-outs
Error: The DDIO_OUT WYSIWYG primitive "bemicro_sys:bemicro_sys_inst|mtx_avalon_sdram_0:the_mtx_avalon_sdram_0|mtx_sdram_controller:sdram|mtx_sdram_ddr_bidir:\gen_ddr_datapath:gen_cyclone_datapath:gen_ddr_dqs_groups:0:gen_gen_ddr_slave_dqs:1:gen_ddr_slave_dqs|altddio_bidir:\gen_ciii_dq:gen_dq_loop:3:ciii_dq|ddio_bidir_86k:auto_generated|ddio_outa[0]" feeding the node "bemicro_sys:bemicro_sys_inst|mtx_avalon_sdram_0:the_mtx_avalon_sdram_0|mtx_sdram_controller:sdram|mtx_sdram_ddr_bidir:\gen_ddr_datapath:gen_cyclone_datapath:gen_ddr_dqs_groups:0:gen_gen_ddr_slave_dqs:1:gen_ddr_slave_dqs|altddio_bidir:\gen_ciii_dq:gen_dq_loop:3:ciii_dq|ddio_bidir_86k:auto_generated|input_cell_h[0]" has multiple fan-outs
...
Altera_Forum
Honored Contributor
14 years ago
Do you have a working project setup with the evaluation IP that you are willing to share?
Altera_Forum
Honored Contributor
14 years ago
Has anyone found a solution for the originally posted problem: Altera's DDR controller yielding
"I/O standard assigned to pin requires VREF value and VREF pin corresponding to pin location not available"
Altera_Forum
Honored Contributor
14 years ago
I'm afraid there is no solution besides either using Microtronix's IP or writing your own.

I haven't tried the former and just as I started the latter, my BeMicro SDK appears to
have died, so that solved my problem :rolleyes:

Hopefully someone will make a new device like it or the micro DE0 when Cyclone V finally
comes out next year.

Tommy
Altera_Forum
Honored Contributor
14 years ago
Thanks for the reply Tommy.

What bugs me about this is it seems the Altera design is imposing an unnecessarily strict IO Standard. The Microtronix IP works fine with the pins defined as standard 1.8V... so why does Altera insist they be SSTL?

If there was some way to disable the check in the Altera IP, could it perhaps be made to work? I wouldn't even know where to look for this, mind you...
Altera_Forum
Honored Contributor
14 years ago
Got some more info to add... check this out:

http://www.altera.com/support/kdb/solutions/rd01042008_479.html?gsa_pos=1&wt.oss_r=1&wt.oss=mobile

"The Cyclone® IV devices use non-DQS read capture whereby the DQS signal is ignored." Which they say doesn't work for Mobile DDR (more details at the page above).

So how does the Microtronix IP work if the Cyclone IV doesn't have the requisite read captuer? By "using the PCIe delay feature and logic elements".

Sounds like they figured out a workaround which uses the PCIe hardware of the Cyclone. Presumably Altera's DDR controller does not contain this workaround.

SO, assuming one wanted to do this themselves... anyone know how to go about "using the PCIe delay feature and logic elements" of the Cyclone IV?

Cheers,
Don

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BeMicro SDK: PIN C6 (VREFB8N0) is assigned to RAM_CS#

17 Replies

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