CAlex
Contributor
ContributorAvalon MM bridge with different time clk
Hi
I'm using cycloneVsoc.
I now want to get data from hps to fpga.
I have two clk ,50MHZ one, which control the FPGA,and a 200 MHZ one control the HPS lwh2f axi bridge.
If I use the avalon mm pipeline bridge ip to connect these two ports, which is correct the bridge IP's clk?
Can bridge IP use the slow clk for the FPGA ? If that is legel, do I need to ,for example, extend the signal from the fast clk region to slow one? Or the bridge IP can handle itself automatically?
Thank you
Reguards
Alex
