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Altera_Forum
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11 years ago

Arrow SoCKit: HSMC_REF_CLK (100MHz) Not Working

@moderator: I found one other thread in this former that mentioned the HSMC_REF_CLK on the Arrow SoCKit and managed to post my question there, but (1) that was somewhat rude to hijack this persons thread and (2) my question is not well publicized. Hence the new thread.

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I have no signal from the HSMC_REF_CLK (100MHz) that should be utilizing Pin 9 (with HCSL I/O Standard). I've tried two Dev Kits, same thing. I even ask a fellow EE next door to try to test the 100MHz clock signal -- he too cannot get a signal from this clock. What Am I missing? If I were to take a simple LED blink module and feed it with the HSMC_REF_CLK (Pin 9 as input), then the module should function? Furthermore, SignalTap is not produce a waveform on this Pin.

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9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    HSMC_REF_CLK is a differential clock. You mention pin 9, but that's only the _p net. The _n net goes to pin 8. I'm guessing you know this - just want to eliminate the obvious.

    Also, there are series resistors on the _p/_n clock nets (R266 and R271). If you have an oscilloscope you can probe the clock on one of those resistors and see if it's active. If it is active then the problem is on your side of things.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Thank you for your response. Correct! I have the input (Pin 9) setup as HCSL I/O standard in Quartus, which automatically assigns Pin 8 as the _n (and I confirmed this is actually happening). We have also probed the resistors and the clocks are not active... and this is on multiple boards. Either the Si5338 devices are not configured properly by the manufacturer of the dev kit, or Quartus does not like how we have the inputs setup and is driving the signal low. There is still some unknowns.

    I'm curious to know if anyone else has a similar issue with the Arrow SoC Kit (Rev. C and Rev. D).

    R/

    Nick
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Definitely sounds like a problem with the Si5338. I'm using that part on a current project (custom board design, not the SoCKit). If the part is not programmed with a default configuration before being soldered to the board then it comes up with all outputs disabled and needs to be initialized via I2C. The I2C interface is controlled by the SoC on SoCKit, so at least you have the ability to fix this. The thing has a ton of registers but the ClockBuilder software from Silicon Labs is pretty easy to use and generates the register values for you.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Thanks for the input! We were hoping to make this quick and easy without having to configure the device, but that may change :-)

    However, we do have a new data point that suggests the Si5338 device is working properly. When we do not include Pin 9 as an input in the Quartus design file and probe the resistor, the 100MHz clock is working. So something in the Quartus design file is driving the input low... to my knowledge, we have set everything up the way it is supposed to be (as mentioned above). Just for sanity checks, I've tried every I/O standard, and different settings within the Pin Planner, but still no change.

    Maybe we should start from square one, because I feel I might be overlooking something obvious: If one were to use a differential clock, how would configure their Quartus design file? Let's start there...
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I am very sorry because I think that I was wrong in my thread.

    I have compiled several designs and tested them with the TSE. At least, the one which was working (with internal FIFO of course) was the one where I took the clock from PIN AF 14 (50MHz) and feed it to a PLL and finally to the pcs_ref. The one with the hsmc_ref_clk can probe the driver but transmission is not working (which seems to be the problem you mention here). With all these files on my hard drive, I properly mixed some files and that was leading me to this error.

    So, as far as I understand: The clock is only working if you not assign it in Quartus? If you have found a solution, I would be interested, too. Obviously I need to configure the SI5338Q anyway.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Thank you for clarifying! Something in Quartus is causing the signal to be driven low when it is assigned... I'm hoping someone can provide us with an easy fix.

    In the meantime, we have downloaded the Clockbuilder software from Si and we are going to see if we can configure the clock.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    OK. I was already in contact with Terasic and they gave me the NVM Register file for the SoCKit and a link to a reference design where the SI5338Q is configured. The design is for a different board but can be easily adaptes...I think. I will try it in the next days. Also, the C Code is available.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Is the NVM Register file freely available? If so, I'd like a copy of that! Also, the link the Si5338Q reference design would be helpful.

    I did see a Wiki that had some C code for the Si5338Q, but I want to configure the device from hardware instead of software (if possible).
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Please send me a private message with your email address ( I am not able to do it until I have made 10 posts)

    The reference design uses a NIOS II and a software solution. We maybe should try this first because it is easier instead oft pure hardware