Honored ContributorIs Arria V GX Starter Kit (http://www.altera.com/products/devkits/altera/kit-arria-v-starter.html) really available?
I tried to contact Altera sales but they said they don't have this board in their database? The same reply from distributor. Also, does anybody know about dev board(s) with Arria V GZ?
Honored ContributorHi all,
I am trying to evaluate the Arria V GX whether it will meet the speed requirements for my design, supposing to run on the Arria V GX Starter Kit. I am using Altera Web edition but this one doesn't seem to support Arria V GX. In the web documentation of the full edition of Quartus I don't see the Arria V GX neither (it has Arria V and Arria V GZ but not GX). The license price is too high just for trying and concluding it might not suit my design. How did you guys compile your designs? BR, WimHonored ContributorSols, is there a method documented for converting a design using one Arria chip -> the one on the Starter Kit ? I believe you indicate that is what you did.
I can chhange the part number but alos need to map the Starter Kit pin allocation as well.Honored ContributorI need a Nios II running a some C code and movind data to and from the host ( rc ) memory.
I sas through the class on the Arria V Hard PCIe IP today and it seems tha tbetween the PCIe IP and the NIOS II there is quite some logic to handle PCIe protocol. I was thinking that logic was in the Hard PCIe IP. I don't need the streaming performance more the processing ability of the NOPS II to work through a set of descriptors in the host memory. IN the DMA examples , I believe the logic I refer to is in the APP level. For the memory mapped Avalon PCIe IP, is there a mega function that handles the PCIe traffice at the MM Avalon level where data reads and writes to memory are presented as normal bus transactions ? Thanks, Bob.
