Arria V GX Starter Kit

I need a Nios II running a some C code and movind data to and from the host ( rc ) memory.

I sas through the class on the Arria V Hard PCIe IP today and it seems tha tbetween the PCIe

IP and the NIOS II there is quite some logic to handle PCIe protocol.

I was thinking that logic was in the Hard PCIe IP. I don't need the streaming performance

more the processing ability of the NOPS II to work through a set of descriptors in the host memory.

IN the DMA examples , I believe the logic I refer to is in the APP level. For the memory mapped

Avalon PCIe IP, is there a mega function that handles the PCIe traffice at the MM Avalon

level where data reads and writes to memory are presented as normal bus transactions ?

Thanks, Bob.