Arria 10 SoC Development Kit: User I/O

Hello @sstrell,

I'm sorry to say that there are 2 MAX V (U16 and U21) as well as a MAX II (U17). In the example I refered to S3 not SW3. S3 is connected to the first MAX V with the signal USER_PB_FPGA0 and, according to Development Kit User Guide "Table 5-27: I/O Assignments of FPGA I/O Pairs and "Figure 5-8: Control Signal Connection", it must be connected to R5 FPGA pin. Pin is used for DQS as default and the compilation error given suggest that this pin is already used (no further information). The error is not given by Pin planner, as I said in the previous message. I read somewhere that these pins can be used for other purposes even if they are used for DQS. Is this informtion right?

I'm using a blank project with 2 inputs and an only one output in order to familiarize with I/O. I didn't find an example like this for Arria 10 SoC Development Kit.