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Vijay2025's avatar
Vijay2025
Icon for New Contributor rankNew Contributor
8 months ago

Arria 10 FPGA to DDR4

In my custom board, Arria 10 terminated with 4x DDR4 discrete memories. I followed these guidelines - 7.4.4.2. Layout Guidelines

Can anyone tell me what is the required routing length between last DDR4 chip (address/control) to its end parallel termination?

Fpga Devkit

1 Reply

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    7 months ago

    Hi


    I think there is not much restriction for that.

    You need to make sure that termination value is around +/- 10% based on your board simulation.


    Regards,

    Adzim