Arria 10 EMIF example design error

Hi Ram,

Thank you for submitting your question in Intel Community.

I'm Adzim, application engineer will assist you in this forum.

I would like to hear more details about the issue that you're facing right now.

Which example design that you're using currently?

• Is it generated from Quartus?
• Which Quartus version that you are using?

Since you're using Arria 10 GX Development Kit, have you checked the Development Kit with BTS program on DDR4?

"i assume DDR4 calibration was successful but the test failed."

• Yes you are right. The DDR4 calibration does passing but failed in Traffic Generator test.

"do you know any issue with this example design?"

"does it support pll ref clk of 266Mhz for this example design?"

• By right the PLL REF CLK should be able to support 266MHz and I think this is the highest setting when memory clock frequency is 1066MHz.

I can try to replicate the issue from my end when you let me know about the example design details.

You can share some snapshots of the EMIF IP setting or provide the EMIF IP in this forum.

Looking forward for your feedback. Thanks!

Regards,

Adzim