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shager's avatar
shager
Icon for New Contributor rankNew Contributor
5 years ago
Solved

Arria 10 CvP

Hi,

I am currently trying to implement Configuration via Protocol (CvP) for our design on an Arria 10 PCI board.
I managed to make CvP work when I do it once after a machine cold start.
However, when I use CvP a second time (without power-cycling the host machine), the machine becomes unresponsive in that I am not able to communicate with the FPGA any longer over PCIe.
I am not even able to read registers from the PCI configuration space.
The CvP process itself, however, terminates correctly, as specified here: Arria 10 CvP UG

From my unterstanding, it should be possible to do CvP arbitrarily often, at least according to CvP White Paper .

Does anybody have a hint, what the reason for this behaviour could be?
For me, it feels as if the HIP stops working correctly (as I am not even able to read the config space).

Thank you very much!

  • JohnT_Altera's avatar
    JohnT_Altera
    5 years ago

    Hi,


    The white paper you mention is only applicable for V series device. CvP udpate is not supported in Arria 10. So you will need to you partial reconfiguration if you would like to update the core image.


3 Replies

  • JohnT_Altera's avatar
    JohnT_Altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    The white paper you mention is only applicable for V series device. CvP udpate is not supported in Arria 10. So you will need to you partial reconfiguration if you would like to update the core image.


    • shager's avatar
      shager
      Icon for New Contributor rankNew Contributor
      5 years ago

      Hi,

      yes, I am using the same core image that was used after the cold boot to update the FPGA.
      Basically, I want to implement the following use case:

      A. The system boots and the FPGA is configured using the peripheral image stored in flash memory.
      B. After the system has booted, I want to write the core image into the FPGA fabric.
      C. Finally, I want to be able to replace the core image at run time in order to update the FPGA logic.

      I am a bit confused because this white paper suggests that CvP can be used to update the core image at run time arbitrarily often. However, as far as I understand you and the Arria 10 user guide, the Arria 10 can only use CvP once (i.e., between two cold boots) in order to initialize the fabric.
      Logic updates via CvP are definitively not possible and must be done via partial reconfiguration.
      Is that correct?

      Thank you very much!