New ContributorHi,
The white paper you mention is only applicable for V series device. CvP udpate is not supported in Arria 10. So you will need to you partial reconfiguration if you would like to update the core image.
Regular ContributorHi,
May I know when you mention you are performing CvP the second time, are you programming the same core image used during cold boot? The reason is that Arria 10 does not support CvP Update. In order to update the design, you are recommended to use Partial Reconfiguration features.
Please refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_cvp_prop.pdf.
New ContributorHi,
yes, I am using the same core image that was used after the cold boot to update the FPGA.
Basically, I want to implement the following use case:
A. The system boots and the FPGA is configured using the peripheral image stored in flash memory.
B. After the system has booted, I want to write the core image into the FPGA fabric.
C. Finally, I want to be able to replace the core image at run time in order to update the FPGA logic.
I am a bit confused because this white paper suggests that CvP can be used to update the core image at run time arbitrarily often. However, as far as I understand you and the Arria 10 user guide, the Arria 10 can only use CvP once (i.e., between two cold boots) in order to initialize the fabric.
Logic updates via CvP are definitively not possible and must be done via partial reconfiguration.
Is that correct?
Thank you very much!
