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PJais1's avatar
PJais1
Icon for New Contributor rankNew Contributor
6 years ago

Arria 10 : data abort after DDR calibration

Hello,

I am designing Linux OS for our custom board based on Arria 10 SoC.I have build uboot and peripheral rbf image and uploaded them in SD card.In our custom board we have used DDR3 memory at HPS side.

While booting, the console is showing a data abort and prefetch error after DDR calibration:

U-Boot 2014.10 (Sep 19 2019 - 11:13:27)

CPU : Altera SOCFPGA Arria 10 Platform

BOARD : Altera SOCFPGA Arria 10 Dev Kit

I2C: ready

DRAM: WARNING: Caches not enabled

FPGA: writing ghrd_10as066n2.periph.rbf..

FPGA: Early Release Succeeded.

SF: Detected N25Q1024A with page size 256 Bytes, erase size 4 KiB, total 128 MiB

DDRCAL: Success

INFO : Skip relocation as SDRAM is non secure memory

Reserving 2048 Bytes for IRQ stack at: ffe3a6e8

DRAM : 2 GiB

Wdata abort

prefetch aààort

Could anyone please suggest how to remove this error?

Thanks,

Priya

11 Replies

  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    Just to check, when using the DDR4 memory, were you able to boot the Arria 10 successfully?

    Are you using the design from our GHRD?

    Regards.

    • PJais1's avatar
      PJais1
      Icon for New Contributor rankNew Contributor
      6 years ago

      Hello,

      I haven't designed using DDR4 as in our custom design DDR3 is connected at HPS side. Also , I am using the design from example design in SOC EDS embedded folder .

      • PJais1's avatar
        PJais1
        Icon for New Contributor rankNew Contributor
        6 years ago

        Hello,

        In our design we did not had ECC enabled . You might check the design parameters in the quartus tool for the DDR used.