New Contributor
Regular ContributorHi,
Just to check, when using the DDR4 memory, were you able to boot the Arria 10 successfully?
Are you using the design from our GHRD?
Regards.
New ContributorHello,
I haven't designed using DDR4 as in our custom design DDR3 is connected at HPS side. Also , I am using the design from example design in SOC EDS embedded folder .
New ContributorHello,
In our design we did not had ECC enabled . You might check the design parameters in the quartus tool for the DDR used.
Regular ContributorHi,
I've noticed you are using Early IO release feature. This means there should be two .rbf files needed, peripheral and core.
Regular ContributorI recommend that you refer the user guide to use Early IO release feature:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an-a10-soc-fpga-early-io-release.pdf
Regards.
