Apply for FA of EP2C35F672I8N

Hi, Chia Pls. kindly refer to below replies in Yellow, thanks! 1. Please provide full device details. 1.1. Device name: FPGA 1.2. Full part number: EP2C35F672I8N 1.3. Date code:1807 1.4. Lot number:BBD9Y1807U 1.5. Trace code: 1.6. Distributor name: Arrow 2. What is the failure rate? What is the failure rate vs. tested sample? Example: 2 out of 100 units. ---Input Qty 270pcs,Defect Qty 27pcs.Failure Rate 10%. 3. What is the failure symptom? Please elaborate the failure symptom in detail. --The functional test item “F2 test” failure. The “F2 Test”function test item is transparent data port. The following is a partial description. This board simultaneously broadcasts one port of F2 transparent transmission data. Incoming asynchronized data reaches FPGA via level conversion. The data is sampled inside the FPGA, and it is sent to the timeslot cross-connection module. Then the data is transmitted at the rate of 64K through F2 of line overhead. The following figure shows the implementation method. (RJ45 is used as data port) [cid:image004.png@01D454D3.7C593240] 5. How did you determine the failure? Please elaborate the procedures. 1. ---Visual checked no problem found, checked the related voltage and clock no abnormal found。 2. Checked the F2 function relevant signals of “HDRXD_0，HDTXD_0” no problem found. 3. Suspected U301 was abnormal that took 3pcs boards to X-Ray check no problem found. (figure 1) 4. Re-flow U301 functional test was still failed. No problem found in the welding after removed U301(figure2) 5. Replaced the “suspect chip U301” the failure step disappeared with three boards. 6. Remounted the “suspect chip U301” on a known good board, the failure step as same as before. [cid:image001.jpg@01D454D0.36978F20] [cid:image002.jpg@01D454D0.36978F20] Fig1 Fig2 6. Does the failure unit ever working before failure? --Yes, until this failure the chip is normal working. 7. Did they violate solder re-flow temperature profiles, moisture sensitivity? Please provide the re-flow temperature profiles. ---See attached reflow profile for details. 8. Did you swap the failure device to a known good board? Is the failure following the device or board? --- A-B-A swap proved the failure following the device. 9. May I know if this request comes from your side or end customer side? If the request is from end customer, please provide the end customer name. ---FA request from Flex. 10. Is this a prototype build or volume/mass production? ---Mass production. 11. Kindly provide quantitative investigation result that could proof the failure is Intel FPGA induced. ---The same question 5. Regards, Jimmy +86 512 67868800 Ext:2132

Hi, Chia End customer is NOKIA, pls. kindly refer to below replies in yellow, thanks! What kind of function can’t work normally? --- The board simultaneously broadcasts one port of F2 transparent transmission data. Did you encounter any open/short failure? ---Not found open/short failure. Any abnormality on the power rail performance? ---Not found. Any suspected failure pins? ---There are only two signals “HDRXD0_OHP_PGA, HDTXD0_OHP_PGA”,The FPGA pins “R5,AB4” ---Not found failure pins. Regards, Jimmy +86 512 67868800 Ext:2132

Hello Any update for this FA application? Thanks! Regards, Jimmy +86 512 67868800 Ext:2132

Hi, Chia The pins”R5,AB4”,This is the spot of the signals corresponding to the FPGA. Regards, Jimmy +86 512 67868800 Ext:2132