Agilex 7: Not able to access the FPGA fabric from HPS through light weight AXI bus

Hi Teh,

Thanks for the reply.

I have done the below:

i. Modified the device tree in Uboot: socfpga_agilex7.dtsi.

I made the below modification to include the light weight AXI and normal AXI bus access:

In order to make the change, I took reference from the existing device tree implementation in Uboot.

fpga_bridge_lwsoc2fpga: lwsoc2fpgabridge@f9000000 {

#address-cells = <1>;

#size-cells = <0>;

compatible = "gdsys,ihs_axi";

reg = <0xf9000000 0x00200000>;

reg-names = "axi_h2f_lw";

clock-names = "h2f_lw_axi_clock";

resets = <&rst LWHPS2FPGA_RESET>;

little-endian;

init-val = <1>;

u-boot,dm-pre-reloc;

};

fpga_bridge_soc2fpga: soc2fpgabridge@80000000 {

#address-cells = <1>;

#size-cells = <0>;

compatible = "gdsys,ihs_axi", "simple-bus";

reg = <0x80000000 0x40000000>;

reg-names = "axi_h2f";

clock-names = "h2f_axi_clock";

resets = <&rst SOC2FPGA_RESET>;

little-endian;

init-val = <1>; //H2F_AXI_MASTER>;

u-boot,dm-pre-reloc;

};

I am able to enable the bridge using the below command:

bridge enable 0x2 as well as bridge enable 0x3

I created a new DTSI file named my_agilex_fpga.dtsi and include it in the socfpga_agilex7_socdk.dts as below:

#include "my_agilex_fpga.dtsi"

I followed the below page to create the "my_agilex_fpga.dtsi" file:
https://www.rocketboards.org/foswiki/Documentation/HOWTOCreateADevicetreeForAgilexSoC#:~:text=dtsi%20file%20contains%20the%20definition,all%20the%20HPS%20IO%20peripherals.

Kindly let me know whether I am doing things correctly or not.

Best Regards,

SpectralSensors