ContributorAgilex 5: Altera ace5lite CCT CSR
I am trying to send a transaction through DMA using the Altera CCT from a streaming component in the FPGA, to SDRAM.
The transfer works with a UBoot script, but in Linux no changes are registered when reading the memory the DMA should have written its transaction to. I assume it is a firewall issue.
In this guide they use the Intel CCT, in which it is possible to expose the CSR register to the lwhps2fpga connector so as to inform the firewall to let such transactions pass.
However, for the Intel CCT: it does not exist in 25.1, and in Qsys does not allow HDL generation in :
Error: Interconnect is required but is currently not supported for the acelite interface type.
So I want to set the Altera CCT CSR to see if this will allow transactions, but it is not exposed.
Does anyone know how to go about doing such a thing? Or even if I am approaching this issue in the right way?
Many thanks!
K
Hi,
This reference design with Cache Coherency Translator (CCT) Intel® FPGA IP is for the Agilex-7 device.
Altera ACE5-Lite Cache Coherency Translator (CCT) FPGA IP is allowing any AXI-4 Manager to communicate with FPGA-to-HPS ACE5-Lite interface in Agilex™ 5 SoC devices and embed the cacheability and coherency signals to the ACE5-Lite subordinate of HPS.
https://www.intel.com/content/www/us/en/docs/programmable/683130/25-1/use-case-73029.html
Cache Coherency Translator (CCT) Intel® FPGA IP is allowing any AXI-4 Manager to communicate with FPGA-to-HPS ACE-Lite interface in Stratix® 10 or Agilex™ 7 SoC devices and embed the cacheability and coherency settings to the ACE-Lite subordinate of HPS.
https://www.intel.com/content/www/us/en/docs/programmable/683130/25-1/use-case-22704.html
Regards
Tiwari
