Forum Discussion
ContributorAgilex 5: Altera ace5lite CCT CSR
Hi,
This reference design with Cache Coherency Translator (CCT) Intel® FPGA IP is for the Agilex-7 device.
Altera ACE5-Lite Cache Coherency Translator (CCT) FPGA IP is allowing any AXI-4 Manager to communicate with FPGA-to-HPS ACE5-Lite interface in Agilex™ 5 SoC devices and embed the cacheability and coherency signals to the ACE5-Lite subordinate of HPS.
https://www.intel.com/content/www/us/en/docs/programmable/683130/25-1/use-case-73029.html
Cache Coherency Translator (CCT) Intel® FPGA IP is allowing any AXI-4 Manager to communicate with FPGA-to-HPS ACE-Lite interface in Stratix® 10 or Agilex™ 7 SoC devices and embed the cacheability and coherency settings to the ACE-Lite subordinate of HPS.
https://www.intel.com/content/www/us/en/docs/programmable/683130/25-1/use-case-22704.html
Regards
Tiwari
Frequent ContributorHi,
I have tried running this below design and it is generating HDL successfully. Quartus v25.1 is also showing Intel CCT IP in Qsys.
Regards
Tiwari
K606Thanks for your response Tiwari - I will look again at this.
Best,
K
- K606
Hi Tiwari,
Here you can see that in my Quartus 25.1 downloaded version, there is no reference to the intel cache coherency translator IP.
$ quartus_sh --version Quartus Prime Shell Version 25.1.0 Build 129 03/26/2025 SC Pro Edition Copyright (C) 2025 Altera Corporation. All rights reserved.Would you maybe know why?
I initialised this project using the project wizard with the part A5ED065BB32AE4SR0.
Many thanks,
K
