Agilex 5: Altera ace5lite CCT CSR

Hi,

This reference design with Cache Coherency Translator (CCT) Intel® FPGA IP is for the Agilex-7 device.

Altera ACE5-Lite Cache Coherency Translator (CCT) FPGA IP is allowing any AXI-4 Manager to communicate with FPGA-to-HPS ACE5-Lite interface in Agilex™ 5 SoC devices and embed the cacheability and coherency signals to the ACE5-Lite subordinate of HPS.

https://www.intel.com/content/www/us/en/docs/programmable/683130/25-1/use-case-73029.html

Cache Coherency Translator (CCT) Intel® FPGA IP is allowing any AXI-4 Manager to communicate with FPGA-to-HPS ACE-Lite interface in Stratix® 10 or Agilex™ 7 SoC devices and embed the cacheability and coherency settings to the ACE-Lite subordinate of HPS.

https://www.intel.com/content/www/us/en/docs/programmable/683130/25-1/use-case-22704.html

Regards

Tiwari