According to the Intel MAX 10 Clocking and PLL User Guide, there is an option to turn off the internal oscillators, in this case what are the phase noise requirements when using an external oscillator?

Sorry I didn't phrase my question correctly, I am referring to the internal oscillators. What I am trying to find out is the phase noise requirements for the PLLs from the reference clock. I am trying to understand what specifications an oscillator will need to meet to drive the reference clock. Phase noise masks are available for other Intel FPGA boards under PLL and Transceiver specifications but I wasn't able to find it for the MAX 10.