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ItouYoshinobu's avatar
ItouYoshinobu
Icon for New Contributor rankNew Contributor
2 years ago

About TSW14J57EVM,DDR4 constraints

Hello.

I am using an adc12dj5200rf board connected to a TSW14J57EVM board.

I am using TSW14J57revE_DDR_RxOnly_L8_Reconfig_FIRMWARE as a base with modified RTL.

jesd204b-IP included.

Please tell me which file sets the timing constraints regarding DDR4 memory interface.

Fpga Devkit

2 Replies

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,


    Thank you for submitting your question in Intel Community.


    The timing constraint will be set in .SDC file.

    You can check in the Quartus software by navigating to Compilation Report -> Timing Analyzer -> SDC File Lists.


    For EMIF IP, the SDC file usually generated as *_altera_emif_arch_nf_191_*.sdc.

    This file can be found in the EMIF IP file folder at altera_emif_arch_nf_191/synth/ directory.


    Regards,

    Adzim


  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.