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ItouYoshinobu's avatar
ItouYoshinobu
Icon for New Contributor rankNew Contributor
2 years ago

About TSW14J57EVM,DDR4 constraints

Hello. I am using an adc12dj5200rf board connected to a TSW14J57EVM board. I am using TSW14J57revE_DDR_RxOnly_L8_Reconfig_FIRMWARE as a base with modified RTL. jesd204b-IP included. Please tell m...
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AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


Thank you for submitting your question in Intel Community.


The timing constraint will be set in .SDC file.

You can check in the Quartus software by navigating to Compilation Report -> Timing Analyzer -> SDC File Lists.


For EMIF IP, the SDC file usually generated as *_altera_emif_arch_nf_191_*.sdc.

This file can be found in the EMIF IP file folder at altera_emif_arch_nf_191/synth/ directory.


Regards,

Adzim