1G Ethernet - Cyclone III demo board EP3C120F780

The standard nios reference design delivered with the kit is using the PHY chip with a RGMII interface at 1gigabit. IIRC they didn't bother to put SDC constraints and the interface is just working out of pure luck.

No we are using our own custom UDP hardware stack. Running through NIOS was too slow. I am using PLL's to generate phase shifts on the clocks.

Those are the sdc files from the linux example design, you should be able to copy/paste them in your own.

:-PThanks for the post on the SDC files. I wanted to let you know that it turned out to be our fault in the design. It appears that high speed serial inputs should not really be considered synchronous. Our state machine reading in the data at the MAC layer was going into an unknown state. We are using additional DFF's to sync the input data, and using the setting in Altera synthesis for safe state machine recovery. When I have time I will go back and fix the state machine by manually defining all states and the transitions.

hi Daixiwen can u send me setup of working rgmii in 1gmode using tse with sdc

The standard nios design shipped by Altera for the kit includes a working gigabit Ethernet interface.