1G Ethernet - Cyclone III demo board EP3C120F780

:-PThanks for the post on the SDC files. I wanted to let you know that it turned out to be our fault in the design. It appears that high speed serial inputs should not really be considered synchronous. Our state machine reading in the data at the MAC layer was going into an unknown state. We are using additional DFF's to sync the input data, and using the setting in Altera synthesis for safe state machine recovery. When I have time I will go back and fix the state machine by manually defining all states and the transitions.