Forum Discussion
Altera_Forum
Honored Contributor
15 years agoThe standard nios reference design delivered with the kit is using the PHY chip with a RGMII interface at 1gigabit. IIRC they didn't bother to put SDC constraints and the interface is just working out of pure luck.
Are you using the Altera drivers with the Interniche stack? There is a register in the PHY chip to shift the RGMII signals by 90 degres, which can help in some situations. I think the driver does that during setup.