10M02SCE144I7G with 192MHz clock frequency

Dear team,

we have a RS485 communication application running between 2 FPGA boards.

FPGA1 sends a ditital bit stream with 12MBit/s through a RS485 trancseiver to the RS485 transceiver of board 2 where the second FPGA reads in the data.

Currently we are developing with the reference design DKDEV-
10M08E144-B. The bitstream with 12 MBit/s is directly read in through an other port of the FPGA. (Output shorted to input).

The oversampling clock is 192MHz. The 12MHz clock and the 192MHz clock are built with the integrated PLL based on the 50MHz external clock source.

The SDC file consits the following settings:

set_time_format -unit ns -decimal_places 3

create_clock -period 20.000 -name clk_50MHz [get_ports {CLK_50MHZ_IN}]

derive_pll_clocks

Questions:

Are the settings in the SDC file sufficient to have an optimized compiler output?

Which settings in the compiler are necessary to have the best results for this time critical application?

Best regards,

Jochen