Forum Discussion
New Contributor10M02SCE144I7G with 192MHz clock frequency
Dear team,
we have a RS485 communication application running between 2 FPGA boards.
FPGA1 sends a ditital bit stream with 12MBit/s through a RS485 trancseiver to the RS485 transceiver of board 2 where the second FPGA reads in the data.
Currently we are developing with the reference design DKDEV-
10M08E144-B. The bitstream with 12 MBit/s is directly read in through an other port of the FPGA. (Output shorted to input).
The oversampling clock is 192MHz. The 12MHz clock and the 192MHz clock are built with the integrated PLL based on the 50MHz external clock source.
The SDC file consits the following settings:
set_time_format -unit ns -decimal_places 3
create_clock -period 20.000 -name clk_50MHz [get_ports {CLK_50MHZ_IN}]
derive_pll_clocks
Questions:
Are the settings in the SDC file sufficient to have an optimized compiler output?
Which settings in the compiler are necessary to have the best results for this time critical application?
Best regards,
Jochen
Is there any further question on this?
4 Replies
sstrellSuper Contributor
You also require I/O timing constraints: set_input_delay and set_output_delay that specify the maximum and minimum external delays to meet setup and hold timing requirements at the FPGA (inputs) and at the downstream device (outputs).
KennyT_alteraYou may also refer to https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-guidance/max-10.html#tab-blade-1-6 for timing constrain need.
This userguide provide end to end work that you need for the entire journey.
- KennyT_altera
Is there any further question on this?
- KennyT_altera
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