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JRe2s's avatar
JRe2s
Icon for New Contributor rankNew Contributor
1 year ago
Solved

10M02SCE144I7G with 192MHz clock frequency

Dear team, we have a RS485 communication application running between 2 FPGA boards. FPGA1 sends a ditital bit stream with 12MBit/s through a RS485 trancseiver to the RS485 transceiver of board 2 wh...
Board Debug
Fpga Devkit
  • KennyT_altera's avatar
    KennyT_altera
    1 year ago

    Is there any further question on this?


sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
1 year ago

You also require I/O timing constraints: set_input_delay and set_output_delay that specify the maximum and minimum external delays to meet setup and hold timing requirements at the FPGA (inputs) and at the downstream device (outputs).