Forum Discussion
JRe2s
New Contributor
New Contributor10M02SCE144I7G with 192MHz clock frequency
Dear team, we have a RS485 communication application running between 2 FPGA boards. FPGA1 sends a ditital bit stream with 12MBit/s through a RS485 trancseiver to the RS485 transceiver of board 2 wh...
Is there any further question on this?
sstrell
Super Contributor
Super ContributorYou also require I/O timing constraints: set_input_delay and set_output_delay that specify the maximum and minimum external delays to meet setup and hold timing requirements at the FPGA (inputs) and at the downstream device (outputs).
