Forum Discussion
JRe2s
New Contributor
New Contributor10M02SCE144I7G with 192MHz clock frequency
Dear team, we have a RS485 communication application running between 2 FPGA boards. FPGA1 sends a ditital bit stream with 12MBit/s through a RS485 trancseiver to the RS485 transceiver of board 2 wh...
Is there any further question on this?
KennyT_altera
Super Contributor
Super ContributorYou may also refer to https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-guidance/max-10.html#tab-blade-1-6 for timing constrain need.
This userguide provide end to end work that you need for the entire journey.
