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Björne2's avatar
Björne2
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2 years ago
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Synthesizing the HDL that OpenCL aoc creates manually

I'm using the Intel FPGA SDK for OpenCL (aoc) to synthesize bitstreams. The tool creates a directory where it stores all generated HDL files. It think (I think) invokes Quartus to synthesize the desi...
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  • BoonBengT_Altera's avatar
    BoonBengT_Altera
    2 years ago

    Hi @Björne2,


    Noted on the situation, unfortunately there is no such build flow available for either OpenCL or within Quartus to do so.

    The current build flow for OpenCL are via creating the hardware configuration file through the aoc command.

    Desire build flow might be similar to other tools mention above.


    Note: Intel OpenCL are in the deprecated roadmap.


    Best Wishes

    BB


Björne2's avatar
Björne2
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2 years ago

Thanks for your answer but I think you misunderstood. In the directory that aoc generates there are subdirectories called board, ip, kernel_hdl, mem, pcie_ed, qdb, reports, and scripts. Shouldn't it be possible to take what's in these directories and invoke the Quartus tools to create the bitstream myself? I want to do this as a learning exercise.