Stratix 10 MX OpenCL issue multiple constant drivers for net "const_mem_0.avm_fill_waitrequest"

Dear Intel Community,

Its me again,

This time I have a weird Issue.

The OpenCL BSP for the Straatix 10 MX is the Intel one which exposes all HBM Memories as single memory interfaces. not as one common global memory. I have 32 Global memories.

I tried to implement an address based Bankswitching to go from HBM1 to HBM31 and so on.

HBM0 is used for Transmission storage.

Didnt work so far. The Boardtest compiles perfectly.

My kernel compiles and generates a const mem 0 device and errors out with

Error (13264): Can't resolve multiple constant drivers for net "const_mem_0.avm_fill_waitrequest" at kernelwithsearch_sys.v(5016) File: c:/intelFPGASync/stratix_mx/generator/project/project_sys.v Line: 5016

" details from project_sys.v"

generate
   begin:const_mem_0
      logic snoop_clk;
      logic snoop_write;
      logic snoop_overflow;
      logic [22:0] snoop_addr;
      logic [4:0] snoop_burst;
      logic [22:0] cc_addr;
      logic cc_read;
      logic cc_waitrequest;
      logic cc_readdatavalid;
      logic [255:0] cc_readdata;
      logic avm_fill_enable;
      logic avm_fill_read;
      logic avm_fill_write;
      logic [27:0] avm_fill_address;
      logic [255:0] avm_fill_writedata;
      logic [31:0] avm_fill_byteenable;
      logic avm_fill_waitrequest;
      logic [255:0] avm_fill_readdata;
      logic avm_fill_readdatavalid;
      logic [4:0] avm_fill_burstcount;
      logic avm_fill_writeack;
      logic [22:0] avm_fill_address_word;

      // INST const_cache of acl_const_cache
      acl_const_cache
      #(
         .NUMPORTS(1),
         .LOG2SIZE(14),
         .LOG2WIDTH(8),
         .AWIDTH(23),
         .MWIDTH(256),
         .BURSTWIDTH(5),
         .FAMILY("Stratix 10"),
         .ASYNC_RESET(0),
         .SYNCHRONIZE_RESET(1),
         .FORCE1XCLK(1),
         .AVM_READ_DATA_LATENESS(0)
      )
      const_cache
      (
         .clk(clock),
         .clk2x(clock2x),
         .resetn(resetn),
         .fill_addr(avm_fill_address_word),
         .fill_read(avm_fill_read),
         .fill_waitrequest(avm_fill_waitrequest),
         .fill_readdatavalid(avm_fill_readdatavalid),
         .fill_readdata(avm_fill_readdata),
         .flush_cache(SearchDAG_finish),
         .snoop_clk(snoop_clk),
         .snoop_overflow(snoop_overflow),
         .snoop_addr(snoop_addr),
         .snoop_burst(snoop_burst),
         .snoop_write(snoop_write),
         .snoop_ready(),
         .rdport_addr(cc_addr),
         .rdport_read(cc_read),
         .rdport_waitrequest(cc_waitrequest),
         .rdport_readdatavalid(cc_readdatavalid),
         .rdport_readdata(cc_readdata)
      );

      assign snoop_clk = 1'b0;
      assign snoop_write = 1'b0;
      assign snoop_overflow = 1'b0;
      assign snoop_addr = '0;
      assign snoop_burst = '0;
      assign cc_addr = {const_avm_0_address[0][27:5]};
      assign cc_read = {const_avm_0_read[0]};
      assign {const_avm_0_waitrequest[0]} = cc_waitrequest;
      assign {const_avm_0_readdatavalid[0]} = cc_readdatavalid;
      assign {const_avm_0_readdata[0]} = cc_readdata;
      assign avm_fill_address = avm_fill_address_word << 5;
      assign avm_fill_write = 1'b0;
      assign avm_fill_byteenable = '1;
      assign avm_fill_burstcount = 5'b00001;
      assign avm_fill_enable = 1'b1;
   end
   endgenerate

I dont know why this is generated. In the Boardtest it is not generated.

Maybe the compiler tries to cache the memory accesses..... well i understand this but i am not soooo perfect in OpenCL.

If anyone has some information for me... It would be awesome.

I tried to modify the BSP to have a unified continuous memory like on the Stratix 10 SX cards but i was out of luck to achieve it.

Any info on this would be very helpfull.

Many greetings so far.

Thomas