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TLeng2's avatar
TLeng2
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5 years ago

Stratix 10 MX OpenCL issue multiple constant drivers for net "const_mem_0.avm_fill_waitrequest"

Dear Intel Community, Its me again, This time I have a weird Issue. The OpenCL BSP for the Straatix 10 MX is the Intel one which exposes all HBM Memories as single memory interfaces. not as one...
TLeng2's avatar
TLeng2
Icon for New Contributor rankNew Contributor
5 years ago

The best would be to be able to change the BSP from 32 individual mem interfaces to one single Access...

In the BSP for the Stratix SX I have 1 Memory Interface which goes to 2 DDR4 Banks.

<!-- DDR4-2666 -->
<global_mem name="DDR" max_bandwidth="42656" interleaved_bytes="1024" config_addr="0x018">
<interface name="board" port="kernel_mem2" type="slave" width="512" maxburst="16" address="0x000000000" size="0x200000000" latency="240" waitrequest_allowance="6"/>
<interface name="board" port="kernel_mem3" type="slave" width="512" maxburst="16" address="0x200000000" size="0x200000000" latency="240" waitrequest_allowance="6"/>
</global_mem>

In the Stratix MX i have 32 Interfaces which go to 32 Memory Interfaces....

// board_spec.xml

<global_mem name="HBM0" max_bandwidth="16000" interleaved_bytes="512" config_addr="0x018">
<interface name="board" port="kernel_slave_0" type="slave" width="256" maxburst="16" address="0x0" size="0x10000000" latency="240" waitrequest_allowance="6" bsp_avmm_write_ack="1"/>
</global_mem>
<global_mem name="HBM1" max_bandwidth="16000" interleaved_bytes="512" config_addr="0x100">
<interface name="board" port="kernel_slave_1" type="slave" width="256" maxburst="16" address="0x10000000" size="0x10000000" latency="240" waitrequest_allowance="6" bsp_avmm_write_ack="1"/>
</global_mem>
<global_mem name="HBM2" max_bandwidth="16000" interleaved_bytes="512" config_addr="0x104">
<interface name="board" port="kernel_slave_2" type="slave" width="256" maxburst="16" address="0x20000000" size="0x10000000" latency="240" waitrequest_allowance="6" bsp_avmm_write_ack="1"/>
</global_mem>
<global_mem name="HBM3" max_bandwidth="16000" interleaved_bytes="512" config_addr="0x108">
<interface name="board" port="kernel_slave_3" type="slave" width="256" maxburst="16" address="0x30000000" size="0x10000000" latency="240" waitrequest_allowance="6" bsp_avmm_write_ack="1"/>
</global_mem>

......

<global_mem name="HBM31" max_bandwidth="16000" interleaved_bytes="512" config_addr="0x178">
<interface name="board" port="kernel_slave_31" type="slave" width="256" maxburst="16" address="0x1f0000000" size="0x10000000" latency="240" waitrequest_allowance="6" bsp_avmm_write_ack="1"/>
</global_mem>

which is on one side OK for a lot of sollutions. but not usefull in my Sollution.

I tried to change it in the boardspec but without luck.

I know i need to adjust the BSP in Quartus too but wasn't able to.....

<global_mem name="HBM0" max_bandwidth="512000" interleaved_bytes="128" config_addr="0x018">
<interface name="board" port="kernel_slave_0" type="slave" width="256" maxburst="16" address="0x0" size="0x10000000" latency="240" waitrequest_allowance="6" bsp_avmm_write_ack="1"/>
<interface name="board" port="kernel_slave_1" type="slave" width="256" maxburst="16" address="0x10000000" size="0x10000000" latency="240" waitrequest_allowance="6" bsp_avmm_write_ack="1"/>
<interface name="board" port="kernel_slave_2" type="slave" width="256" maxburst="16" address="0x20000000" size="0x10000000" latency="240" waitrequest_allowance="6" bsp_avmm_write_ack="1"/>

......

<interface name="board" port="kernel_slave_31" type="slave" width="256" maxburst="16" address="0x1f0000000" size="0x10000000" latency="240" waitrequest_allowance="6" bsp_avmm_write_ack="1"/>
</global_mem>

I know this BSP exists already somewhere.

DongWang-BJTU's avatar
DongWang-BJTU
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Where did get the this BSP ?

  • TLeng2's avatar
    TLeng2
    Icon for New Contributor rankNew Contributor
    5 years ago

    I got the BSP in January from Intel.

    We bought the Stratix MX Card with it.

    At this point the OpenCL was still on intels roadmap.

    Now it isnt anymore and it seems that we spent 50K$ for Developmentkits for nothing

    • jomarm10's avatar
      jomarm10
      Icon for New Contributor rankNew Contributor
      3 years ago

      Hi,

      I am facing the same issue. We have the same S10MX board and the same BSP... we need bigger buffers.

      We made some failed attempts to group them.

      All we get is

      Error (13224): Verilog HDL or VHDL error at lsu_token_ring.sv(207): $fatal : lsu_ic_top ring interconnect: Multiple write rings are not supported when using BSP_AVMM_WRITE_ACK
      Error (16185): Can't elaborate user hierarchy "freeze_wrapper_inst|pr_region_inst"
      Error (16186): Can't elaborate top-level user hierarchy

      Did you find any solution to this?

      Best Regards.