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TLeng2's avatar
TLeng2
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5 years ago

Stratix 10 MX OpenCL issue multiple constant drivers for net "const_mem_0.avm_fill_waitrequest"

Dear Intel Community, Its me again, This time I have a weird Issue. The OpenCL BSP for the Straatix 10 MX is the Intel one which exposes all HBM Memories as single memory interfaces. not as one...
  • TLeng2's avatar
    TLeng2
    Icon for New Contributor rankNew Contributor
    5 years ago

    Dear EBERLAZARE,

    Thank You for the Information.

    I understand the fact of the too many drivers. The issue is that I dont create the mem0 module.

    I am using the Intel OpenCL for FPGA on this Board and it gets automatically created.

    How can I prevent this ?

    • EBERLAZARE_I_Intel's avatar
      EBERLAZARE_I_Intel
      Icon for Regular Contributor rankRegular Contributor
      5 years ago

      Hi Steffen,

      This problem may comes from the fact that the signal is technically multidrive since it is assigned multiple times as the process is inside a generate block.

      By looking into your source code, you could workaround the problem by taking the some processes out of the generate frame statement.