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LennartVH's avatar
LennartVH
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4 years ago

SDC constraints with native module for OpenCL

I'm creating a native verilog module for use within an OpenCL kernel. I was wondering if it is possible to create SDC constraints for my native module. The openCL compiler does not accept .sdc fi...
LennartVH's avatar
LennartVH
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4 years ago

Thank you, @BoonBengT_Altera

We've been able to solve the issue in a different way, where we transmit the constant over two wires to shift register receivers all across the FPGA. That saves us a lot of routing resources as well.
In any case thank you for the linked document, if the need comes up again we'll definitely consult it.

Kind regards,
Lennart