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LennartVH's avatar
LennartVH
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4 years ago

SDC constraints with native module for OpenCL

I'm creating a native verilog module for use within an OpenCL kernel.

I was wondering if it is possible to create SDC constraints for my native module. The openCL compiler does not accept .sdc files, as it only accepts .v, .vhd, and memory files. Is there a different area where I can specify my constraints?

In particular I wish to create a false path constraint to optimize a near-constant value used throughout the design.

Any ideas?

5 Replies

  • BoonBengT_Altera's avatar
    BoonBengT_Altera
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    4 years ago

    Hi @LennartVH,

    Thank you for posting in Intel community forum and hope all is well.
    Unfortunately per my understanding SDC should be added in the quartus project level.


    Hence you will need to proceed to quartus design to do so.
    Please do let us know if I misunderstand the situation.

    Best Wishes
    BB

  • LennartVH's avatar
    LennartVH
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    4 years ago

    Thanks for replying,

    The issue is that working with OpenCL, I cannot edit the generated Quartus Project itself. It is generated by aoc in the process of an OpenCL compile, from an xml file that describes the module. In that xml I must specify the files that are needed for my module: verilog files, vhd files, memory files, etc. And then when it compiles it just copies the necessary files to a fresh Quartus Project and executes the necessary tcl scripts for OpenCL compilation. The thing is that it's really picky about the accepted file types, accepting only these files, and not for example .qip files or .sdc files. I was just looking to see if there's a workaround I can use, even perhaps going as far as using filesystem events to detect and edit the generated top.sdc before quartus reads it.

    Kind regards,
    Lennart

  • LennartVH's avatar
    LennartVH
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    3 years ago

    Thank you, @BoonBengT_Altera

    We've been able to solve the issue in a different way, where we transmit the constant over two wires to shift register receivers all across the FPGA. That saves us a lot of routing resources as well.
    In any case thank you for the linked document, if the need comes up again we'll definitely consult it.

    Kind regards,
    Lennart

  • BoonBengT_Altera's avatar
    BoonBengT_Altera
    Icon for Moderator rankModerator
    3 years ago

    Hi @LennartVH,


    Good to know that you managed workaround the issues and appreciate the sharing of the steps. Sure please feel free to get in touch with us for any clarification. As there is no further clarification on this thread, we will no longer monitor this thread.

    Thank you for the questions and as always pleasure having you here.


    Best Wishes

    BB