Forum Discussion
ContributorHBM - high band memory
ContributorHi Adzim,
Then, I tried to create example design from scratch again ( HBM location -top )
but still I got error:
Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 UFIND4H_UIB(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error(175001): The Fitter cannot place 1 UFIND4H_UIB, which is within High Bandwidth Memory (HBM2) Interface Intel FPGA IP ed_synth_hbm_0_example_design_altera_hbm_1961_g23n22y.
Info(14596): Information about the failing component(s):
Info(175028): The UFIND4H_UIB name(s): hbm_0_example_design|hbm_0_example_design|uib|arch_inst|ufi_inst|ufi_inst
Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error(175006): There is no routing connectivity between source HBMC and the UFIND4H_UIB
Info(175026): Source: HBMC hbm_0_example_design|hbm_0_example_design|uib|arch_inst|hbmc_inst|hbmc_inst
Info(175021): The source HBMC was placed in location HBMC_X95_Y2_N1
Error(175022): The UFIND4H_UIB could not be placed in any location to satisfy its connectivity requirements
Info(175029): 1 location affected
Info(175029): UFIND4HUIB_X95_Y292_N0
Just want to remind that when the HBM location define in the Bottom everything works correctly
Do you have idea how can I solve it ?
Contributorwant to add to my previous post :
your archive project works fine and compile successfully in my workspace ,
but when I try to create from scratch example design ( HBM location -top ) still I get error
- ymiler
Hi
good news!!
I found the root cause of the error :
Error(175001): The Fitter cannot place 1 UFIND4H_UIB, which is within High Bandwidth Memory (HBM2) Interface Intel FPGA IP ed_synth_hbm_0_example_design_altera_hbm_1961_g23n22y
It was my set_location_assignment pin clock to PIN_AR26 - when remove it the Quartus succeed to finish the Plan stage successfully
But , Why ? this is legal pin ?
In addition , when the HBM is located at the bottom there is no issue even the assignment of the PIN_AR26
Are there more problematic pins when the HBM locate at the top ?
- ymiler
Hi
I found the issue
the solution is here :
Place this reference clock input on the UIB_PLL_REF_CLK_00 pins while using the HBM2 device on the bottom of the FPGA, or the UIB_PLL_REF_CLK_01 pins while using the HBM2 on the top of the FPGA.
when I locate the right pin it works
