Occasional Contributor
Occasional ContributorThanks @yuguen for clarifying the content of add.sv
However I had followed the instructions and after I issue "make report" the following files are generated (there is no add.sv but rather add_report_di.sv which internally has a different module name and subsequently Quartus complains about missing top node. Why do I get add_report_di.sv rather than add.sv?
-rw-rw-r-- 1 tetto tetto 527 Feb 19 17:08 sys_description.txt -rw-rw-r-- 1 tetto tetto 3831 Feb 19 17:08 sys_description.legend.txt -rw-rw-r-- 1 tetto tetto 1860 Feb 19 17:08 sys_description.hex -rw-rw-r-- 1 tetto tetto 105 Feb 19 17:08 opencl.ipx -rw-rw-r-- 1 tetto tetto 4758 Feb 19 17:08 kernel_system.v -rw-rw-r-- 1 tetto tetto 3388 Feb 19 17:08 kernel_system.tcl -rw-rw-r-- 1 tetto tetto 7882 Feb 19 17:08 kernel_system.qip -rw-rw-r-- 1 tetto tetto 31 Feb 19 17:08 kernel_system_import.tcl -rw-rw-r-- 1 tetto tetto 70 Feb 19 17:08 kernel_report.tcl -rw-rw-r-- 1 tetto tetto 1197 Feb 19 17:08 ipinterfaces.xml -rw-rw-r-- 1 tetto tetto 72 Feb 19 17:08 ip_include.tcl -rw-rw-r-- 1 tetto tetto 28 Feb 19 17:08 compiler_metrics.out -rw-rw-r-- 1 tetto tetto 1197 Feb 19 17:08 board_spec.xml -rw-rw-r-- 1 tetto tetto 0 Feb 19 17:08 add_report.v -rw-rw-r-- 1 tetto tetto 3759 Feb 19 17:08 add_report_sys.v -rw-rw-r-- 1 tetto tetto 18924 Feb 19 17:08 add_report_sys_hw.tcl -rw-rw-r-- 1 tetto tetto 231 Feb 19 17:08 add_report.log -rw-rw-r-- 1 tetto tetto 19180 Feb 19 17:08 add_report_di.sv -rw-rw-r-- 1 tetto tetto 1307 Feb 19 17:08 add_report_di_inst.v -rw-rw-r-- 1 tetto tetto 17892 Feb 19 17:08 add_report_di_hw.tcl -rw-rw-r-- 1 tetto tetto 8393 Feb 19 17:08 add_report.bc.xml drwxrwxr-x 2 tetto tetto 4096 Feb 19 17:08 ip drwxrwxr-x 3 tetto tetto 4096 Feb 19 17:08 reports drwxrwxr-x 3 tetto tetto 4096 Feb 19 17:08 kernel_hdl drwxrwxr-x 3 tetto tetto 4096 Feb 19 17:08 include drwxrwxr-x 3 tetto tetto 4096 Feb 19 17:08 linux64
Also in the instruction it is sad to copy these:
cp add-quartus-sln/add.sv add-quartus $> cp add-quartus-sln/jtag.sdc add-quartus
but after "make report" the folder add-quartus-sln is not there, so also miss jtag.sdc
Occasional ContributorHey @StefanoC,
When doing "make report", you are generating RTL for the SYCL code that is in the add-oneapi folder.
This RTL top module can indeed be found in "add_report_di.sv".
This is the IP that you need to integrate into an existing RTL pipeline.
The "add_quartus_sln" folder already contains RTL, and is there to mimic your own RTL pipeline. So the "add.sv" file is already there, before you do "make report" as this is not a generated file, this is the existing RTL pipeline. You can peak into this file and see it is making a led turn on on the FPGA based on another signal. This is not possible to express using SYCL.
This tutorial shows how to connect the generated RTL from SYCL (the add_report_di.sv IP) with the existing "add.sv" RTL pipeline.
So "add" from add.sv is the top level module, that depends on the SYCL generated RTL.
The steps in the README tells you to:
1/ generate the SYCL IP
Create a Quartus project with the existing RTL files:
This also sets the top level module to "add" which is contained in the add.sv that was just copied from add-quartus-sln
Then, import the SYCL generated IP:
Then connects the two in the following steps, etc.
Occasional ContributorOk @yuguen now I better understand the workflow, and I could make progress thanks to your explanation.
Unfortunately I am stuck at the last step of the tutorial as I am on the Cyclone10 (while the tutorial is for Arria) so when setting the pins I really don't know which ones to select (PIN_AM10 does not exist on the Cyclone10). Also I feel I would need the a file jtag.sdc made for Cyclone10 (I cannot seem to find it here: https://github.com/altera-opensource/ghrd-socfpga)
On a slightly different note, I tried to modify the C++ source file adding arrays to be added (rather than primitive int), in my new add_kernel_wrapper I observe I got an "Avalon Memory Mapped Host" while previously (like in the tutorial) I only had "Avalon Memory Mapping Agent"); I wonder how the new "Avalon Memory Mapped Host" should be connected, as generating the HDL I see warning about "Avalon Memory Mapped Host" must be connected to an Avalon-MM agent or exported.
ContributorHi Stefano,
Can you please share what board you are using?
I will assume you are using the Terasic Cyclone 10 GX devkit. There are some sample designs here: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=253&No=1147&PartNo=3#contents
According to the user guide in there, there are 2 100MHz clocks you can use, C10_CLKUSR and C10_REFCLK2:
As far as the JTAG.sdc, I can't find one to use for that devkit, but it is not strictly necessary for functionality. The timing analyzer will complain about timing failure since it will try to constrain the JTAG lines but I think you can ignore those warnings.
Occasional Contributoryes I am using the Cyclone 10GX, the link you provided contains various things but I do not see any oneAPI example. So far I think I am near to having a working sample using the "add" tutorial (https://github.com/oneapi-src/oneAPI-samples/tree/master/DirectProgramming/C%2B%2BSYCL_FPGA/Tutorials/Tools/platform_designer/add-oneapi/src based on the Arria board), I will just provide the pin clock you suggested and bypass the jtag.sdc
