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Re: 25.3 PRO Release
Hi Arun, There is a utility called `lsusb` that you can add to your Yocto image. Add the following IMAGE_INSTALL line to gsrd-socfpga/agilex5_dk_a5e065bb32aes1-gsrd-rootfs/conf/local.conf: # CONF_VERSION is increased each time build/conf/ changes incompatibly and is used to # track the version of this file when it was generated. This can safely be ignored if # this doesn't mean anything to you. CONF_VERSION = "2" # support lsusb IMAGE_INSTALL:append = " usbutils" Then rebuilt your SD card image with bitbake gsrd-console-image The output I see when the PNY USB stick I linked above is plugged in: root@agilex5dka5e065bb32aes1:~# lsusb --tree /: Bus 001.Port 001: Dev 001, Class=root_hub, Driver=xhci-hcd/1p, 480M /: Bus 002.Port 001: Dev 001, Class=root_hub, Driver=xhci-hcd/1p, 10000M |__ Port 001: Dev 002, If 0, Class=Mass Storage, Driver=usb-storage, 5000M root@agilex5dka5e065bb32aes1:~# This shows that there are 2 USB hosts, and that bus 2 is the USB 3 host. If you poll the devices and look at usb2 instead of usb1, we see USB 3 compatibility. root@agilex5dka5e065bb32aes1:~# cat /sys/devices/platform/soc\@0/11000000.usb1/xhci-hcd.0.auto/usb2/2-1/version 3.20Re: 25.3 PRO Release
Hello Arun, thanks for sharing. I suspect the problem is your USB to Type C connector; those adapters can sometimes silently downgrade USB speeds. I tested using a USB mass storage device that has both a USB-A and a USB-C port, and I verified USB SS speeds using CrystalDiskMark and fio. PNY DUO LINK V3 USB 3.2 Gen 2 Dual Flash Drive I've attached the logs I see when I attach this USB Stick: root@agilex5e:~# dmesg | grep USB [ 1.480973] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1 [ 1.510119] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2 [ 1.517753] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.1 Enhanced SuperSpeed [ 1.525956] hub 1-0:1.0: USB hub found [ 1.542405] hub 2-0:1.0: USB hub found [ 4.732358] usbhid: USB HID core driver [ 37.071576] usb 1-1: new high-speed USB device number 2 using xhci-hcd [ 37.446512] usb-storage 1-1:1.0: USB Mass Storage device detected [ 38.497114] scsi 0:0:0:0: Direct-Access PNY USB 3.2.2 FD PMAP PQ: 0 ANSI: 6 During U-Boot: SOCFPGA_AGILEX5 # usb start starting USB... Bus usb@10b00000: Port not available. Bus usb31@11000000: probe failed, error -110 No USB controllers found scanning usb for storage devices... 0 Storage Device(s) found SOCFPGA_AGILEX5 # Please note that I built this Linux image using the newer GSRD 2.0 (tested with Quartus® Prime 25.3), which uses Kas to manage Yocto layers, but the Linux configurations should be the same as the 'classic' GSRD. Rebuilding GSRD 2.0 BinariesRe: 25.3 PRO Release
Hello Arun, thanks for your question. I assume you are following our guide to enable USB 3.1 device mode on the Agilex™ 5 HPS for the Agilex™ 5 E-series premium devkit. Please note that this guide only started working in Quartus® Prime 25.1.1; not 25.1. USB 3.1 Gen-1 Controller Tutorial Example Design User Guide How can you tell that the Agilex™ 5 devkit is detected as USB 2.0? I checked the device using USBTreeView and it enumerated as USB 3.2 Gen 1 (which, confusingly, is basically the same thing as USB 3.1 Gen 1 and USB 3.0). Are you sure the upstream port you connected to supports USB 3.1?Re: EPCS64 access from HPS on Cyclone V
Hi Naresh, I discussed your issue with a colleague, and we studied the schematic for your devkit: https://www.terasic.com.tw/cgi-bin/page/archive_download.pl?Language=English&No=1211&FID=ed51cec1fd3eff2414308b716a4a21fe Given that the EPCS is connected to the active serial pins on the Cyclone V, it is only accessible during configuration. Since you hav chosen to configure via FPPx32, you cannot access the EPCS once the HPS has booted.Re: Questions about mSGDMA
Hello Anpeng, thanks for posting. In Chapter 31 of the Embedded Peripherals IP User Guide, there is a section that mentions that you need to commit the descriptor information using the 'go' bit in the control field (bit 127). 31.4.6. Control Field In your modelsim screenshot, I can see that bit 127 is clear, can you try setting it?Re: Failed to debug the SMP cycloneVsoc boards
Hi CAlex, thanks for the post. I've got a few questions to help me debug this issue. Do you have a sample project you can upload so that I can check your settings and try and reproduce? Which board and version of Quartus tools are you using? How can you tell that the cores are suspended, are you just looking at a message in ArmDS?Re: II is an approximation due to the following stallable instructions
Hello! You can learn about this in the loop_initiation_interval tutorial and the kernel_args_restrict tutorial. Basically, you need to tell the compiler that the kernel arguments don't alias with the kernel_args_restrict attribute: struct FunctorKernel { // ------------------------------------------- // Kernel interface definition. // ------------------------------------------- [[intel::kernel_args_restrict]] void operator()() const { // ---------------------------------------- // Kernel code implementation. // ---------------------------------------- } };Re: regarding-intel high level synthesis
Hello. You can use the HLS Pro edition with Quartus® Prime Standard Edition. https://www.intel.com/content/www/us/en/docs/programmable/683680/23-1/installing-the-pro-edition-on-linux-systems.html oneAPI is indeed the current recommended tool for creating FPGA IP. You can use oneAPI 2025.0 on Windows and Linux if you wish to create FPGA IP. If you wish to create and execute FPGA Acceleration workloads, you must use a supported Linux distribution. https://www.intel.com/content/www/us/en/developer/articles/system-requirements/intel-oneapi-dpcpp-system-requirements.html You can learn more on our homepage or our customer journey: https://www.intel.com/content/www/us/en/developer/tools/oneapi/fpga.html https://www.intel.com/content/www/us/en/support/programmable/support-resources/guided-journey/agilex5/oneapi-fpga.html
