Forum Discussion
Hi @DorianL,
Noted with thanks for the details explanation for the error, and you are right unfortunately the current IP authoring compilation flow are build and supporting only for Quartus Pro edition, hence the error that you are seeing could be part of that reason. Would recommend to try with Quartus Pro edition instead. Please do let us know if there is other things we could help with.
Hope that clarify.
Best Wishes
BB
Hi @BoonBengT_Altera ,
I tried to simulate with a version of Quartus Prime Pro edition but I still have the same issue, I can't simulate Streaming pipes in my IPs whereas it is working when I use MMHost pipes or Conduit pipes. I tried to simulate with fpga_sim command the example "Vector_add" on the github oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/hls_flow_interfaces/component_interfaces_comparison/pipes but it is not working, is it simulating for you ? Do you have an idea of what could be responsible of that ? Thank you !
- DorianL2 years ago
New Contributor
Hi,
I tried with the new version of oneAPI 2024.1 and it finally worked ! Thank you for your help.
DorianL