Intel MAX 10 FPGA 10M02SCE144I7G, RAM Inference issue

The following doesn't infer RAM:

Dummy_test_infer_RAM : single_port_ram GENERIC MAP(ADDR_WIDTH=> address_bits, DATA_WIDTH=>8) port map (we=> (PCI_CSx and not_R_W), clk =>clock, addr=> dummy_addr , q => dummy_q, data => dummy_data);--

<< Tried synchronous and asynchronous RAM>>

-- q <= ram(addr_reg);-- location

It seams it infer the RAM if I set the file containing "single_port_ram" as Top-Level Entity, otherwise being called ("Dummy_test_infer_RAM :[…]" see above)

from the main file as Top-Level Entity, it doesn't infer.

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.std_logic_unsigned.all;

entity single_port_ram is

generic

(

DATA_WIDTH : natural := 8;

ADDR_WIDTH : natural := 6

);

port

(

clk : in std_logic;

addr : in natural range 0 to 2**ADDR_WIDTH - 1;

data : in std_logic_vector((DATA_WIDTH-1) downto 0);

we : in std_logic := '1';

q : out std_logic_vector((DATA_WIDTH -1) downto 0)

);

end entity;

architecture rtl of single_port_ram is

-- Build a 2-D array type for the RAM

subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);

type memory_t is array((2**ADDR_WIDTH)-1 downto 0) of word_t;

-- Declare the RAM signal.

signal ram : memory_t;

attribute ramstyle : string;

attribute ramstyle of ram : signal is "MLAB, no_rw_check";--MLAB

attribute max_depth : natural;

attribute max_depth of ram : signal is 1024;

-- Register to hold the address

signal addr_reg : natural range 0 to 2**ADDR_WIDTH-1;

--set_instance_assignment -name RAMSTYLE_ATTRIBUTE LOGIC -to ram;

--set_global_assignment ram INFER_RAMS_FROM_RAW_LOGIC on;

-- (* ramstyle = "mlab" *) ram ;

-- (* max_depth = 512 *) reg [7:0] ram[0:63];

begin

process(clk)

begin

if(rising_edge(clk)) then

if(we = '1') then

ram(addr) <= data;

else

addr_reg <= addr;

q <= ram(addr_reg);--

end if;

-- Register the address for reading

-- addr_reg <= addr;

-- q <= ram(addr_reg);--

end if;--if(rising_edge(clk)) then

end process;

-- q <= ram(addr_reg);--

end rtl;

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

package single_port_ram_package is

component single_port_ram

generic

(

DATA_WIDTH : natural := 8;

ADDR_WIDTH : natural := 6

);

port

(

clk : in std_logic;

addr : in natural range 0 to 2**ADDR_WIDTH - 1;

data : in std_logic_vector((DATA_WIDTH-1) downto 0);

we : in std_logic := '1';

q : out std_logic_vector((DATA_WIDTH -1) downto 0)

);

end component;

end single_port_ram_package;