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SVasi8
New Contributor
New ContributorIntel MAX 10 FPGA 10M02SCE144I7G, RAM Inference issue
The following doesn't infer RAM: Dummy_test_infer_RAM : single_port_ram GENERIC MAP(ADDR_WIDTH=> address_bits, DATA_WIDTH=>8) port map (we=> (PCI_CSx and not_R_W), clk =>clock, addr=> dummy_addr , ...
SVasi8New Contributor
New ContributorHi Richard,
Did I send this info to the right place?
Thanks,
Regards,
Stel
RichardT_altera
Super Contributor
Super ContributorSorry for the late response but I do not see any attached file. Could you share the file again?
