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SVasi8's avatar
SVasi8
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6 years ago

Intel MAX 10 FPGA 10M02SCE144I7G, RAM Inference issue

The following doesn't infer RAM: Dummy_test_infer_RAM : single_port_ram GENERIC MAP(ADDR_WIDTH=> address_bits, DATA_WIDTH=>8) port map (we=> (PCI_CSx and not_R_W), clk =>clock, addr=> dummy_addr , ...
RichardT_altera's avatar
RichardT_altera
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6 years ago

Hi,

I am not able to find information related to this error and could not duplicate the error as well.

Could you help to share the project that could duplicate this error? A simplified project will do.

  • SVasi8's avatar
    SVasi8
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    6 years ago
    Hi Richard, Please see attached a simplified version. Since then I found that “true_dual_port_ram_single_clock” does infer, but still it looks as the RAM doesn’t work. I have replaced for synchronous and a- synchronous version q_b <= ram(addr_reg_b); with q_b<= x"AA"; and does read out, so seems that the MUX and signals to read out works. Thanks, Regards, Stel
  • SVasi8's avatar
    SVasi8
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    6 years ago
    Hi, Any feedback on this? Thanks, Regards, Stel
  • SVasi8's avatar
    SVasi8
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    6 years ago
    Hi Richard, Did I send this info to the right place? Thanks, Regards, Stel
    • RichardT_altera's avatar
      RichardT_altera
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      6 years ago

      Sorry for the late response but I do not see any attached file. Could you share the file again?

    • SVasi8's avatar
      SVasi8
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      6 years ago
      Hi, See attached , Regards, Stel
  • SVasi8's avatar
    SVasi8
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    5 years ago
    Hi Richard, Any feedback on this? Thanks, Regards, Stel