Forum Discussion
Intel FPGA AI Sutie Inference Engine
Is there any official documentation on the DLA runtime or inference engine for managing the DLA from the ARM side? I need to develop a custom application for running inference, but so far, I’ve only found the dla_benchmark (main.cpp) and streaming_inference_app.cpp example files. There should be some documentation covering the SDK. The only documentation that i found related with is the Intel FPGA AI suite PCIe based design example https://www.intel.com/content/www/us/en/docs/programmable/768977/2024-3/fpga-runtime-plugin.html
From what I understand, the general inference workflow involves the following steps:
- Identify the hardware architecture
- Deploy the model
- Prepare the input data
- Send inference requests to the DLA
- Retrieve the output data
42 Replies
- JohnT_Altera
Regular Contributor
Hi,
Yes, your understanding is correct where you should be able to continuously feed new data for inference. Your understanding of accelerator is correct.
- RubenPadial
Contributor
Hello @JohnT_Intel ,
Is there any news about this topic?
I'm using the S2M design in case it is helpful to find an alternative solution based on streaming app.
- JohnT_Altera
Regular Contributor
Hi Ruben,
Unfortunately I do not have the setup to this up and I am working with engineering to see how we can implement the flow that you requested.
I am sorry if I am not able expediate this support and I am trying my best to help you resolved the issue.
- RubenPadial
Contributor
Hello @JohnT_Intel,
Sorry. As you suggested reusing the inference request instead of creating a new one for each inference, I thought the solution was trivial and that the problem was in my implementation or concept.
I look forward to a solution.
I believe the concept of using the DLA is correct in a real application: deploy the accelerator and configure it with the graph, then keep it configured and continuously feed it with new data for inference. Isn't that right? Of course, new inferences must wait for the previous one to finish. Is this correct, or have I misunderstood something about the working principle of the accelerator?
- RubenPadial
Contributor
Hello @JohnT_Intel ,
I only commented out the // Flip Vertically and // Group the data into 9 slaves sections to avoid excessively extending the log, as they only modify the already retrieved output. You can run the full code if you’d like. Do you have any questions about that?
The raw output is printed in the previous section, as you can see in the log file.
Again, do you have an example or pseudocode for properly handling the inference requests?
- JohnT_Altera
Regular Contributor
Hi Ruben,
From the output log file, I observed that it is different from your code where certain printout is missing.
I do not observed the print out below.
// Flip Vertically
flipHorizontally(processed_output);
std::cout << "Flipped Output Array:" << std::endl;
for (const auto& row : processed_output) {
std::cout << "[ ";
for (const auto& value : row) {
std::cout << value << " ";
}
std::cout << "]" << std::endl;
}
// Group the data into 9 slaves
std::vector<std::vector<int>> grouped_output = groupData(processed_output);
std::cout << "\nGrouped Output Array:" << std::endl;
for (size_t i = 0; i < grouped_output.size(); ++i) {
std::cout << "Group " << i + 1 << ": [ ";
for (const auto& value : grouped_output[i]) {
std::cout << value << " ";
}
std::cout << "]" << std::endl;
}
std::cout << "RIS Resolution: " << output_shape[3] << "-bit." << std::endl;
std::vector<int> flattened_output;
for (const auto& group : grouped_output) {
flattened_output.insert(flattened_output.end(), group.begin(), group.end());
}
// std::vector<uint64_t> groups = prepareData(flattened_output, output_shape[3]);
std::vector<uint64_t> groups = prepareData(grouped_output, output_shape[3]);
std::cout << "Prepared Data for SPI:" << std::endl;
for (size_t i = 0; i < groups.size(); ++i) {
std::cout << "Group " << i << ": 0x"
<< std::hex << groups[i]
<< std::dec << std::endl;
}
const std::string throughput_file_name = "throughput_report.txt";
std::ofstream throughput_file;
throughput_file.open(throughput_file_name);
throughput_file << "Throughput : " << totalFps << " fps" << std::endl;
throughput_file << "Batch Size : " << batchSize << std::endl;
throughput_file << "Graph number : " << exeNetworks.size() << std::endl;
throughput_file << "Num Batches : " << num_batches << std::endl;
throughput_file.close();
// Output Debug Network Info if COREDLA_TEST_DEBUG_NETWORK is set
ReadDebugNetworkInfo(ie);
if (return_code) return return_code;
Thanks.
John Tio
- JohnT_Altera
Regular Contributor
Hi,
it seems like you are creating a new inference request for every new input, and it failed at the 6th. Instead of creating a new inference request for every new input, you should keep using the same set of inference requests, wait for one to become available, and supply input data to it.
- RubenPadial
Contributor
Hello @JohnT_Intel
,Do you have an example or pseudocee?
- JohnT_Altera
Regular Contributor
Hi Ruben,
If that is the case then I suspect that the FPGA AI suite might not be able to run as it is already pre-occupied with the previous inferencing. It has already not able to run further inferencing unless the previous task is already fully completed and it can move towards a new inferencing.
- RubenPadial
Contributor
Hello @JohnT_Intel ,
Yes, that's what I supposed. How should it be handled?
The inferRequest->wait(), inferRequest->startAsync() and inferRequestsQueue->waitAll() statements are used, and the output is properly retrieved, so the inference is completed. I don't know what happens with the request or how to handle/wait/stop the request once inference is finished.
- JohnT_Altera
Regular Contributor
Hi Ruben,
Can I confirm that you are running below command multiple time where the 6 times, you are facing the error?
./ris_app \
-arch_file=$arch \
-cm=$model \
-plugins_xml_file=$plugins \
-nireq=1 \
-niter=1 \
-d=HETERO:FPGA,CPU
- RubenPadial
Contributor
Hello @JohnT_Intel ,
No, I run it once. In the application there is a loop from step 9 to 11. In the 6th iteration of the loop program fails.
Prior stepts to 9 are intended to configure the dla and create the dla instance. The aim of looping steps 9 to 11 is to continually request inference to the already configured dla.
- JohnT_Altera
Regular Contributor
Hi Ruben,
I check on the log provided but it does not provide the full information on how you run it. Is it running the same graph? Or can you provide the step you use to run the application?
- RubenPadial
Contributor
Hello @JohnT_Intel ,
Same grpah with nireq and niter set to 1 in every inference.
This is how I run the application:
./ris_app \
-arch_file=$arch \
-cm=$model \
-plugins_xml_file=$plugins \
-nireq=1 \
-niter=1 \
-d=HETERO:FPGA,CPU
As far as I know, I only used the graph once to configure the DLA, and then I continually request inferences to that instance. At least that was the objective.
- JohnT_Altera
Regular Contributor
Hi Ruban,
Sorry that I forget to check which FPGA AI Suite version are you running? As the latest FPGA AI Suite (2024.3) runtime application code is different to yours.
- RubenPadial
Contributor
Hello @JohnT_Intel,
I'm currently using FPGA AI Suite 2023.2 and OpenVINO 2022.3.1. I know it is no the latest rlease of FPGA AI Suite but I cannot move the project to FPGA AI Suite 2024.3 at this moment.
- JohnT_Altera
Regular Contributor
Hi,
Can you also the full log when you are running it multiple time until you observed the error?
- RubenPadial
Contributor
Hello @JohnT_Intel,
Here it is: https://consigna.ugr.es/?s=download&token=0fcf80b0-8ff5-47da-8da7-5b9acebf1646As you can see with the debug lines I included, program fails in line "inferRequestsQueues.push_back(std::move(
std::unique_ptr<InferRequestsQueue>(new InferRequestsQueue(*exeNetwork, nireq))));" in the 6th iteration.