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BJian12's avatar
BJian12
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6 years ago

In Q18.1 and A10 FPGA，Whether can I capture the PERST de-assertion and image loading complete in the signaltap？

1 Reply

  • Nathan_R_Intel's avatar
    Nathan_R_Intel
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    6 years ago

    Yes, you could capture the PERST de-assertion using signaltap for Arria 10 FPGA.

    Regards,

    Nathan