New ContributorI want to create one FPGA version (one gbs file) that will consist of my RTL files and an OpenCL file that will accelerate into the FPGA (by OpenCL Kernel compiler).
How can i do it?
New ContributorWhat I mean is how to add interfaces such as HSSI besides the existing PCI, DDR and my RTL files.
Frequent ContributorAn OpenCL kernel compiled with the OpenCL compiler will directly connect to the interfaces defined in the OpenCL BSP. If your RTL needs access to FPGA I/O, then you should add that to the OpenCL BSP and recreate the BSP, which will be a difficult task. If, however, your RTL does not need to access FPGA I/O, you can convert it to an RTL library as describe in Intel FPGA SDK for OpenCL's guides, and then directly instantiate that library in an OpenCL kernel. The last option is to convert your OpenCL kernel to an HLS kernel and compile it using Intel's HLS compiler into an HDL module and then integrate it with your existing RTL module and other necessary IP cores through Qsys.
New ContributorFirst of all, thank you!
I need connect my RTL to IO. I need to connect it to a 10G MAC.
Also I need DDR too.
Do you know a guide that explains how to do this?
Maybe reverse? Maybe there is a way to insert the OpenCL compiler result into the AFU environment that I created as a FPGA developer.
Super ContributorYou can try modify the ref design to suite your needs. You can look into https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/opencl-bsp-support.html for more information
New ContributorThank you!
